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Formal equivalence checking
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== References == *''Electronic Design Automation For Integrated Circuits Handbook'', by Lavagno, Martin, and Scheffer, {{ISBN|0-8493-3096-3}} A survey of the field. This article was derived, with permission, from Volume 2, Chapter 4, ''Equivalence Checking'', by Fabio Somenzi and Andreas Kuehlmann. *R.E. Bryant, ''[https://apps.dtic.mil/sti/pdfs/ADA470446.pdf Graph-based algorithms for Boolean function manipulation]'', IEEE Transactions on Computers., C-35, pp. 677β691, 1986. The original reference on BDDs. *Sequential equivalence checking for RTL models. Nikhil Sharma, Gagan Hasteer and Venkat Krishnaswamy. [http://www.eetimes.com/document.asp?doc_id=1271433 EE Times].
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