Editing Front-side bus (section)

==Evolution==

The front-side bus had the advantage of high flexibility and low cost when it was first designed. Simple [[symmetric multiprocessor]]s place a number of CPUs on a shared FSB, though performance could not scale linearly due to bandwidth [[wikt:bottleneck|bottlenecks]].

The front-side bus was used in all [[Intel Atom]], [[Celeron]], [[Intel P5 (microarchitecture)|Pentium]], [[Core 2]], and [[Xeon]] processor models through about 2008<ref>{{cite web | url=https://www.anandtech.com/show/2458 | title=Intel X38 Tango - is High FSB Overclocking Worth It? }}</ref> and was eliminated in 2009.<ref>{{cite web | url=https://www.guru3d.com/review/core-i7-975-review/page-4/ | title=Core i7 975 review (Page 4) | date=2 June 2009 }}</ref> Originally, this bus was a central connecting point for all system devices and the CPU.

The potential of a faster CPU is wasted if it cannot fetch instructions and data as quickly as it can execute them. The CPU may spend significant time idle while waiting to read or write data in main memory, and high-performance processors therefore require high bandwidth and low latency access to memory. The front-side bus was criticized by [[AMD]] as being an old and slow technology that limits system performance.<ref>{{cite web |title= AMD HyperTransport Bus: Transport Your Application to Hyper Performance |date= September 29, 2003 |author= Allan McNaughton |publisher= AMD |url= http://developer.amd.com/documentation/articles/Pages/929200370.aspx |access-date= June 14, 2011 |archive-url= https://web.archive.org/web/20120325070619/http://developer.amd.com/documentation/articles/Pages/929200370.aspx |archive-date= March 25, 2012 |url-status= dead }}</ref>

More modern designs use point-to-point and serial connections like AMD's [[HyperTransport]] and Intel's [[Direct Media Interface|DMI 2.0]] or [[Intel QuickPath Interconnect|QuickPath Interconnect]] (QPI). These implementations remove the traditional [[Northbridge (computing)|northbridge]] in favor of a direct link from the CPU to the system memory, high-speed peripherals, and the [[Platform Controller Hub]], [[Southbridge (computing)|southbridge]] or I/O controller.<ref name="QPI">{{cite web |title= An Introduction to the Intel QuickPath Interconnect |date= January 30, 2009 |publisher= Intel Corporation |url= http://www.intel.com/technology/quickpath/introduction.pdf |access-date= June 14, 2011 }}</ref><ref>{{cite web | url=https://arstechnica.com/gadgets/2009/09/intel-launches-all-new-pc-architecture-with-core-i5i7-cpus/ | title=Intel launches all-new PC architecture with Core i5/I7 CPUs | date=8 September 2009 }}</ref><ref>{{cite web | url=https://www.guru3d.com/review/core-i7-975-review/page-4/ | title=Core i7 975 review (Page 4) | date=2 June 2009 }}</ref>

In a traditional architecture, the front-side bus served as the immediate data link between the CPU and all other devices in the system, including main memory. In HyperTransport- and QPI-based systems, system memory is accessed independently by means of a [[memory controller]] integrated into the CPU, leaving the bandwidth on the HyperTransport or QPI link for other uses. This increases the complexity of the CPU design but offers greater throughput as well as superior scaling in multiprocessor systems.