Editing Instruction cycle (section)

==Summary of stages==
Source:<ref>{{Cite book |url=https://collegedata.blob.core.windows.net/facultynotes22odd/602-unit%204.pdf |title=Instruction Timing and Cycle}}</ref>

Each computer's CPU can have different cycles based on different instruction sets, but will be similar to the following cycle:

# '''Fetch stage''': The fetch stage initiates the instruction cycle by retrieving the next instruction from memory. During this stage, the PC is polled for the address of the instruction in memory (using the MAR). Then the instruction is stored from the MDR into the CIR. At the end of this stage, the PC points to the next instruction that will be read at the next cycle.
# '''Decode stage''': During this stage, the encoded instruction in the CIR is interpreted by the CU. It determines what operations and additional operands are required for execution and sends respective signals to respective components within the CPU, such as the ALU or FPU, to prepare for the execution of the instruction.
# '''Execute stage''': This is the stage where the actual operation specified by the instruction is carried out by the relevant functional units of the CPU. Logical or arithmetic operations may be run by the ALU, data may be read from or written to memory, and the results are stored in registers or memory as required by the instruction. Based on output from the ALU, the PC might branch.
# '''Repeat cycle'''

In addition, on most processors, [[Interrupt|interrupts]] can occur. This will cause the CPU to jump to an interrupt service routine, execute that, and then return to the instruction it was meant to be executing. In some cases, the instruction can be interrupted in the middle, but there will be no effect, and the instruction will be re-executed after return from the interrupt.