Editing Intel i960 (section)

===80960CA, 80960CF===
The {{vanchor|i960CA}} was announced in July 1989. It featured a newly designed superscalar RISC core and added an unusual addressable on-chip cache, but lacked an FPU and MMU, as it was intended for high-performance embedded applications. The i960CA is widely considered<ref>{{cite book |last1=Shen |first1=John Paul |last2=Lipasti |first2=Mikko H. |title=Modern Processor Design: Fundamentals of Superscalar Processors |date=2003 |publisher=McGraw Hill |isbn=0-07-282968-0 |page=328 |edition=Beta}}</ref> to have been the first single-chip [[superscalar]] RISC implementation. The C-series included only one ALU, but could dispatch and execute an arithmetic instruction, a memory reference, and a branch instruction at the same time, and sustain two instructions per cycle under certain circumstances. The first versions released ran at 33&nbsp;MHz, and Intel promoted the chip as capable of 66 MIPS. The i960CA microarchitecture was designed in 1987–1988 and formally announced on September 12, 1989.

Later, in May 1992, came the i960CF, which included a larger instruction cache (4 KB instead of 1 KB) and added 1 KB of data cache, but was still without an FPU or MMU.