Editing Itanium (section)

=== Itanium 2 (McKinley and Madison): 2002–2006 ===
{{Infobox CPU
 | name=Itanium 2 (McKinley and Madison)
 | image=KL Intel Itanium2.jpg
 | image_size=300px
 | caption=Itanium 2 processor
 | produced-start=8 July 2002
 | produced-end=16 November 2007{{refn|McKinley: 16 April 2004<ref>{{cite web |title=Product Change Notification |url=http://developer.intel.com/design/pcn/Processors/D0103649.pdf |publisher=Intel |archive-url=https://web.archive.org/web/20040719080318/http://developer.intel.com/design/pcn/Processors/D0103649.pdf |archive-date=2004-07-19 |url-status=dead}}</ref><br/>Madison 6M: 28 July 2006<ref>{{cite web |title=Product Change Notification |url=http://developer.intel.com/design/pcn/Processors/D0105835.pdf |publisher=Intel |archive-url=https://web.archive.org/web/20060313054448/http://developer.intel.com/design/pcn/Processors/D0105835.pdf |archive-date=2006-03-13 |url-status=dead}}</ref><br/>Madison 9M: 16 November 2007<ref>{{cite web |title=Product Change Notification |url=https://qdms.intel.com/dm/i.aspx/53B15559-69D6-4DD5-8379-0ABE33DCE8D4/PCN107564-00.pdf |publisher=Intel.<br/>Warning: forced download |access-date=28 April 2022}}</ref>}}
 | slowest=900
 | fastest=1667
 | slow-unit=
 | fast-unit=MHz
 | fsb-slowest=400
 | fsb-fastest=667
 | fsb-slow-unit=
 | fsb-fast-unit=MT/s
 | hypertransport-slowest=
 | hypertransport-fastest=
 | hypertransport-slow-unit=
 | hypertransport-fast-unit=
 | size-from=[[180 nm]]
 | size-to=[[130 nm]]
 | soldby=
 | designfirm=[[Hewlett-Packard|HP]] and Intel
 | manuf1=
 | core1=
 | sock1=[[PAC611]]
 | pack1=
 | brand1=
 | arch=
 | microarch=
 | cpuid=
 | code=McKinley, Madison, Deerfield, Madison&nbsp;9M, Fanwood
 | numcores=1
 | l1cache=
 | l2cache=256&nbsp;KB
 | l3cache=1.5–9&nbsp;MB
 | application=
}}

The '''Itanium 2''' processor was released in July 2002, and was marketed for enterprise servers rather than for the whole gamut of high-end computing. The first Itanium&nbsp;2, code-named ''McKinley'', was jointly developed by HP and Intel, led by the HP team at [[Fort Collins, Colorado]], [[tape-out|taping out]] in December 2000. It relieved many of the performance problems of the original Itanium processor, which were mostly caused by an inefficient memory subsystem by approximately halving the latency and doubling the fill bandwidth of each of the three levels of cache, while expanding the L2 cache from 96 to 256 KB. Floating-point data is excluded from the L1 cache, because the L2 cache's higher bandwidth is more beneficial to typical floating-point applications than low latency. The L3 cache is now integrated on-chip rather than on a separate die, tripling in associativity and doubling in bus width.  McKinley also greatly increases the number of possible instruction combinations in a VLIW-bundle and reaches 25% higher frequency, despite having only eight pipeline stages versus Merced's ten.<ref>{{cite web |last1=Hammond |first1=Gary |last2=Naffziger |first2=Sam |title=Next Generation Itanium™ Processor Overview |url=http://intel.com/design/itanium2/download/McK-IDF-2001.pdf |archive-url=https://web.archive.org/web/20030706123550/http://intel.com/design/itanium2/download/McK-IDF-2001.pdf |archive-date=6 July 2003 |url-status=dead}}</ref><ref name="HP_McKinley_wp"/>

''McKinley'' contains 221 million transistors (of which 25 million are for logic and 181 million for L3 cache), measured 19.5&nbsp;mm by 21.6&nbsp;mm (421&nbsp;mm<sup>2</sup>) and was fabricated in a 180&nbsp;nm, bulk CMOS process with six layers of aluminium metallization.<ref>{{cite journal |last1=Naffzinger |first1=Samuel D. |first2=Glenn T. |last2=Colon-Bonet |first3=Timothy |last3=Fischer |first4=Reid |last4=Riedlinger |first5=Thomas J. |last5=Sullivan |first6=Tom |last6=Grutkowski |date=November 2002 |title=The implementation of the Itanium&nbsp;2 microprocessor |journal=[[IEEE Journal of Solid-State Circuits]] |volume=37 |issue=11 |pages=1448–1460 |doi=10.1109/JSSC.2002.803943 |bibcode=2002IJSSC..37.1448N |url=http://cpus.hp.com/technical_references/jssc_naffziger.pdf|archive-url=https://web.archive.org/web/20030322045555/http://cpus.hp.com/technical_references/jssc_naffziger.pdf |archive-date=2003-03-22 |url-status=dead}}</ref><ref>{{cite web |last1=Soltis |first1=Don |last2=Gibson |first2=Mark |title=Itanium® 2 Processor Microarchitecture Overview |url=http://www.hotchips.org/archives/hc14/2_Mon/03_soltis.pdf |website=[[Hot Chips]] |archive-url=https://web.archive.org/web/20050531030015/http://www.hotchips.org/archives/hc14/2_Mon/03_soltis.pdf |archive-date=31 May 2005 |url-status=dead}}</ref><ref>{{cite web |last1=Naffziger |first1=Samuel |last2=Hammond |first2=Gary |title=The Implementation of the Next-Generation 64b Itanium Microprocessor |url=http://www.imec.be/elela/HD03/examens/2003/D20_6.pdf |archive-url=https://web.archive.org/web/20041029174655/http://www.imec.be/elela/HD03/examens/2003/D20_6.pdf |archive-date=29 October 2004 |url-status=dead}}</ref> In May 2003 it was disclosed that some McKinley processors can suffer from a critical-path erratum leading to a system's crashing. It can be avoided by lowering the processor frequency to 800&nbsp;MHz.<ref>{{cite web |last1=Krazit |first1=Tom |title=Intel details Itanium 2 bug |url=https://www.computerworld.com/article/2570015/intel-details-itanium-2-bug.html |website=[[Computerworld]] |date=12 May 2003 |access-date=30 March 2022}}</ref>

In 2003, [[Advanced Micro Devices|AMD]] released the [[Opteron]] CPU, which implements its own [[64-bit computing|64-bit]] architecture called [[AMD64]]. The Opteron gained rapid acceptance in the enterprise server space because it provided an easy upgrade from [[x86]]. Under the influence of Microsoft, Intel responded by implementing AMD's x86-64 [[instruction set architecture]] instead of IA-64 in its [[Xeon]] microprocessors in 2004, resulting in a new industry-wide ''de facto'' standard.<ref name="cautionary"/>

In 2003, Intel released a new Itanium&nbsp;2 family member, codenamed ''Madison'', initially with up to 1.5&nbsp;GHz frequency and 6 MB of L3 cache. The ''Madison 9M'' chip released in November 2004 had 9 MB of L3 cache and frequency up to 1.6&nbsp;GHz, reaching 1.67&nbsp;GHz in July 2005. Both chips used a 130&nbsp;nm process and were the basis of all new Itanium processors until Montecito was released in July 2006, specifically ''Deerfield'' being a low wattage ''Madison'', and ''Fanwood'' being a version of ''Madison 9M'' for lower-end servers with one or two CPU sockets.

In November 2005, the major Itanium server manufacturers joined with Intel and a number of software vendors to form the Itanium Solutions Alliance to promote the architecture and accelerate the software porting effort.<ref name="ISA">{{cite web
 |url          = http://www.itaniumsolutionsalliance.org
 |title        = Itanium Solutions Alliance
 |access-date   = May 16, 2007
 |work         = ISA web site
 |archive-url  = https://web.archive.org/web/20080908015727/http://www.itaniumsolutionsalliance.org/
 |archive-date = September 8, 2008
 |url-status   = usurped
 |df           = mdy-all
}}</ref>
The Alliance announced that its members would invest $10 billion in the Itanium Solutions Alliance by the end of the decade.<ref>{{cite web
 |url         = http://www.ednasia.com/article-12139-computingleadersannouncestrategyforneweraofmissioncriticalcomputing-Asia.html
 |title       = Computing Leaders Announce Strategy for New Era of Mission Critical Computing
 |access-date  = October 16, 2008
 |last        = Scott
 |first       = Bilepo
 |date        = January 26, 2006
 |work        = Itanium Solutions Alliance Press Release
 |archive-url  = https://web.archive.org/web/20120111011444/http://www.ednasia.com/article-12139-computingleadersannouncestrategyforneweraofmissioncriticalcomputing-Asia.html
 |archive-date = January 11, 2012
 |url-status  = dead
 |df          = mdy-all
}}</ref>