Editing List of file formats (section)

=== Electronic design automation (EDA) ===
[[Electronic design automation]] (EDA), or electronic computer-aided design (ECAD), is specific to the field of electrical engineering.
* BRD – Board file for [[EAGLE (program)|EAGLE Layout Editor]], a commercial [[Printed circuit board|PCB]] design tool
* [[Boundary scan description language|BSDL]] – Description language for testing through [[JTAG]]
* CDL – [[Transistor]]-level [[netlist]] format for [[Integrated circuit|IC]] design
* [[Common Power Format|CPF]] – Power-domain specification in [[system-on-a-chip]] (SoC) implementation (see also [[Unified Power Format|UPF]])
* [[Design Exchange Format|DEF]] – [[Logic gate|Gate]]-level [[Integrated circuit layout|layout]]
* Detailed Standard Parasitic Format – Detailed Standard Parasitic Format, [[Analog signal|Analog]]-level Parastic component of interconnections in [[Integrated circuit|IC]] design
* [[EDIF]] – Vendor neutral [[Logic gate|gate]]-level [[netlist]] format
* FSDB – [[Analog waveform]] format (see also [[Waveform viewer]])
* [[GDSII]] – Format for [[Printed circuit board|PCB]] and [[Integrated circuit layout|layout]] of integrated circuits
* [[Intel HEX|HEX]] – [[ASCII]]-coded [[Binary file|binary]] format for [[memory dump]]s
* LEF – Library Exchange Format, physical abstract of cells for [[Integrated circuit|IC]] design
* Liberty (EDA) – [[Library (electronics)#Library|Library]] modeling ([[Logic function|function]], timing) format
* MS12 – [[NI Multisim]] file
* OASIS – [[Open Artwork System Interchange Standard]]
* [[OpenAccess]] – Design database format with [[Application Programming Interface|API]]s
* PSF – Cadence proprietary format to store simulation results/waveforms (2GB limit)
* PSFXL – Cadence proprietary format to store simulation results/waveforms
* SDC – Synopsys Design Constraints, format for [[Logic synthesis|synthesis]] constraints
* [[Standard Delay Format|SDF]] – Standard for [[Logic gate|gate]]-level timings
* [[Standard Parasitic Exchange Format|SPEF]] – Standard format for Parasitic component of interconnections in [[Integrated circuit|IC]] design
* SPI, CIR – [[SPICE]] Netlist, device-level [[netlist]] and commands for [[Computer simulation|simulation]]
* [[SREC (file format)|SREC]], S19 – S-record, [[ASCII]]-coded format for [[memory dump]]s
* SST2 – Cadence proprietary format to store mixed-signal simulation results/waveforms
* STIL – Standard Test Interface Language, IEEE1450-1999 standard for Test Patterns for [[Integrated circuit|IC]]
* SV – [[SystemVerilog]] source file
* S*P – [[Touchstone file|Touchstone]]/[[EEsof]] Scattering parameter data file – multi-port blackbox performance, measurement or simulated 
* [[Timing Library Format|TLF]] – Contains timing and logical information about a collection of cells ([[circuit element]]s)
* [[Unified Power Format|UPF]] – Standard for Power-domain specification in [[System-on-a-chip|SoC]] implementation
* V – [[Verilog]] source file
* [[Value Change Dump|VCD]] – Standard format for [[Digital data|digital]] simulation [[waveform]]
* VHD, VHDL – [[VHDL]] source file
* WGL – Waveform Generation Language, format for Test Patterns for [[Integrated circuit|IC]]