Editing Logic synthesis (section)

==References==
{{Reflist|refs=
<ref name="Verilog_2005">{{cite web|url=https://ocw.mit.edu/courses/electrical-engineering-and-computer-science/6-884-complex-digital-systems-spring-2005/lecture-notes/l05_synthesis.pdf|title=Synthesis:Verilog to Gates}}</ref>
<ref name="Sherwani_1999">{{cite book|author=Naveed A. Sherwani|title=Algorithms for VLSI physical design automation|year=1999|edition=3rd|page=4|publisher=Kluwer Academic Publishers|isbn=978-0-7923-8393-2}}</ref>
<ref name="EETimes_2017">EETimes: [http://archives.eetimes.com/high-level-synthesis-rollouts-enable-esl/110436.html High-level synthesis rollouts enable ESL]{{dead link|date=May 2017 |bot=InternetArchiveBot |fix-attempted=yes }}</ref>
}}
* ''Electronic Design Automation For Integrated Circuits Handbook'', by Lavagno, Martin, and Scheffer, {{ISBN|0-8493-3096-3}} A survey of the field of [[Electronic design automation]]. The above summary was derived, with permission, from Volume 2, Chapter 2, ''Logic Synthesis'' by Sunil Khatri and Narendra Shenoy.