Editing Microarchitecture (section)

=== Instruction set choice ===
Instruction sets have shifted over the years, from originally very simple to sometimes very complex (in various respects). In recent years, [[load–store architecture]]s, [[Very long instruction word|VLIW]] and [[Explicitly Parallel Instruction Computing|EPIC]] types have been in fashion. Architectures that are dealing with [[data parallelism]] include [[Single instruction, multiple data|SIMD]] and [[Vector processor|Vectors]]. Some labels used to denote classes of CPU architectures are not particularly descriptive, especially so the CISC label; many early designs retroactively denoted "[[complex instruction set computer|CISC]]" are in fact significantly simpler than modern RISC processors (in several respects).

However, the choice of [[instruction set architecture]] may greatly affect the complexity of implementing high-performance devices. The prominent strategy, used to develop the first RISC processors, was to simplify instructions to a minimum of individual semantic complexity combined with high encoding regularity and simplicity. Such uniform instructions were easily fetched, decoded and executed in a pipelined fashion and a simple strategy to reduce the number of logic levels in order to reach high operating frequencies; instruction cache-memories compensated for the higher operating frequency and inherently low [[code density]] while large register sets were used to factor out as much of the (slow) memory accesses as possible.