Editing NaN (section)

=== Encoding ===
In [[IEEE&nbsp;754]] interchange formats, NaNs are identified by specific, pre-defined bit patterns unique to NaNs. The sign bit does not matter. For the binary formats, NaNs are represented with the exponent field filled with ones (like infinity values), and some non-zero number in the trailing significand field (to make them distinct from infinity values). The original IEEE&nbsp;754 standard from 1985 ([[IEEE&nbsp;754-1985]]) only described binary floating-point formats, and did not specify how the signaling/quiet state was to be tagged. In practice, the most significant bit of the trailing significand field determined whether a NaN is signaling or quiet. Two different implementations, with reversed meanings, resulted:
* most processors (including those of the [[Intel]] and [[AMD]]'s [[x86]] family, the [[Motorola 68000 series|Motorola 68000 family]], the [[AIM alliance|AIM]] [[PowerPC]] family, the [[ARM architecture|ARM]] family, the [[Sun Microsystems|Sun]] [[SPARC]] family, and optionally new [[MIPS architecture|MIPS]] processors) set the signaling/quiet bit to non-zero if the NaN is quiet, and to zero if the NaN is signaling. Thus, on these processors, the bit represents an {{code|is_quiet}} flag;
* in NaNs generated by the [[PA-RISC]] and old MIPS processors, the signaling/quiet bit is zero if the NaN is quiet, and non-zero if the NaN is signaling. Thus, on these processors, the bit represents an {{code|is_signaling}} flag.
The former choice has been preferred as it allows the implementation to quiet a signaling NaN by just setting the signaling/quiet bit to 1. The reverse is not possible with the latter choice because setting the signaling/quiet bit to 0 could yield an infinity.<ref>{{cite web|url=https://grouper.ieee.org/groups/1788/email/msg03272.html|title=Re: (long) sNaNs not what they could be...|website=[[IEEE]]|date=15 October 2010|access-date=5 November 2020}}</ref>

The [[IEEE 754-2008 revision|2008]] and 2019 revisions of the IEEE&nbsp;754 standard make formal requirements and recommendations for the encoding of the signaling/quiet state.
* For binary interchange formats, the most significant bit of the trailing significand field is exclusively used to distinguish between quiet and signaling NaNs.<ref>{{Harvnb|IEEE 754|2019|loc=§3.4}}</ref> (This requirement has been added in the 2019 revision.) Moreover, it should be an {{code|is_quiet}} flag.<ref>{{Harvnb|IEEE 754|2019|loc=§6.2.1}}</ref> That is, this bit is non-zero if the NaN is quiet, and zero if the NaN is signaling.
* For decimal interchange formats, whether binary or decimal encoded, a NaN is identified by having the top five bits of the combination field after the sign bit set to ones. The sixth bit of the field is the {{code|is_signaling}} flag. That is, this bit is zero if the NaN is quiet, and non-zero if the NaN is signaling.<ref>{{Harvnb|IEEE 754|2019|loc=§3.5.2}}</ref>

For IEEE&nbsp;754-2008 conformance, the meaning of the signaling/quiet bit in recent MIPS processors is now configurable via the NAN2008 field of the FCSR register. This support is optional in MIPS Release&nbsp;3 and required in Release&nbsp;5.<ref>{{cite web|url=http://cdn2.imgtec.com/documentation/MD00083-2B-MIPS64INT-AFP-05.04.pdf|title=MIPS Architecture For Programmers – Volume I-A: Introduction to the MIPS64 Architecture|date=20 November 2013|publisher=MIPS Technologies, Inc.|page=79|access-date=27 September 2017}}</ref>

The state of the remaining bits of the trailing significand field are not defined by the standard. These bits encode a value called the 'payload' of the NaN. For the binary formats, the encoding is unspecified. For the decimal formats, the usual encoding of unsigned integers is used. If an operation has a single NaN input and propagates it to the output, the result NaN's payload should be that of the input NaN (this is not always possible for binary formats when the signaling/quiet state is encoded by an {{code|is_signaling}} flag, as explained above). If there are multiple NaN inputs, the result NaN's payload should be from one of the input NaNs; the standard does not specify which.