Editing Nios II (section)

=== Nios II/f ===
The Nios II/f core is designed for maximum performance at the expense of core size. Features of Nios II/f include:
* Separate instruction and data caches (512&nbsp;[[byte|B]] to 64&nbsp;[[kilobyte|KB]])
* Optional [[memory management unit|MMU]] or [[Memory protection unit|MPU]]
* Access to up to 2&nbsp;[[gigabyte|GB]] of external address space
* Optional tightly coupled memory for instructions and data
* Six-stage pipeline to achieve maximum [[DMIPS]]/MHz
* Single-cycle hardware multiply and barrel shifter
* Optional hardware divide option
* Dynamic [[branch predictor|branch prediction]]
* Up to 256 custom instructions and unlimited hardware accelerators
* [[JTAG]] debug module
* Optional JTAG debug module enhancements, including hardware breakpoints, data triggers, and real-time trace