Editing Phase-locked loop (section)

==Applications==
Phase-locked loops are widely used for [[synchronization]] purposes; in space [[telecommunications|communications]] for [[coherent demodulation]] and [[threshold extension]], [[bit synchronization]], and symbol synchronization. Phase-locked loops can also be used to [[demodulate]] [[frequency modulation|frequency-modulated]] signals. In radio transmitters, a PLL is used to synthesize new frequencies which are a multiple of a reference frequency, with the same stability as the reference frequency.<ref name=":0">{{Cite book |last1=Khalili Dermani |first1=M. |last2=Baghaei |first2=M. S. |last3=Colas |first3=Frédéric |last4=Rioual |first4=Michel |last5=Guillaud |first5=Xavier |last6=Retiere |first6=Nicolas |title=CIRED Porto Workshop 2022: E-mobility and power distribution systems |chapter=Non-linear stability analysis of the electrical vehicle chargers power stage connected to the weak grid |date=2022 |url=https://digital-library.theiet.org/content/conferences/10.1049/icp.2022.0855 |language=en |publisher=Institution of Engineering and Technology |pages=955–959 |doi=10.1049/icp.2022.0855 |isbn=978-1-83953-705-9|s2cid=251122708 }}</ref>

Other applications include:
* [[Demodulation]] of [[frequency modulation]] (FM): If PLL is locked to an FM signal, the VCO tracks the instantaneous frequency of the input signal. The filtered error voltage which controls the VCO and maintains lock with the input signal is demodulated FM output. The VCO transfer characteristics determine the linearity of the demodulated out. Since the VCO used in an integrated-circuit PLL is highly linear, it is possible to realize highly linear FM demodulators. 
* Demodulation of [[frequency-shift keying]] (FSK): In digital data communication and computer peripherals, binary data is transmitted by means of a carrier frequency which is shifted between two preset frequencies.
* Recovery of small signals that otherwise would be lost in noise ([[lock-in amplifier]] to track the reference frequency)
* Recovery of clock timing information from a data stream such as from a [[disk drive]]
* [[CPU multiplier|Clock multipliers]] in [[microprocessors]] that allow internal processor elements to run faster than external connections, while maintaining precise timing relationships
* Demodulation of [[modem]]s and other tone signals for [[telecommunications]] and [[remote control]].
* [[Digital signal processing|DSP]] of [[video]] signals; Phase-locked loops are also used to synchronize phase and frequency to the input [[analog video]] signal so it can be [[sample (signal)|sampled]] and digitally processed
* [[Atomic force microscopy]] in [[Non-contact atomic force microscopy#Frequency modulation|frequency modulation]] mode, to detect changes of the cantilever resonance frequency due to tip–surface interactions
* [[DC motor]] [[motor controller|drive]]

===Clock recovery===
Some data streams, especially high-speed serial data streams (such as the raw stream of data from the magnetic head of a disk drive), are sent without an accompanying clock. The receiver generates a clock from an approximate frequency reference, and then uses a PLL to phase-align it to the data stream's [[signal edge]]s. This process is referred to as [[clock recovery]]. For this scheme to work, the data stream must have edges frequently-enough to correct any drift in the PLL's oscillator. Thus a [[line code]] with a hard upper bound on the maximum time between edges (e.g. [[8b/10b encoding]]) is typically used to encode the data.

===Deskewing===
If a clock is sent in parallel with data, that clock can be used to sample the data. Because the clock must be received and amplified before it can drive the flip-flops which sample the data, there will be a finite, and process-, temperature-, and voltage-dependent delay between the detected clock edge and the received data window. This delay limits the frequency at which data can be sent. One way of eliminating this delay is to include a deskew PLL on the receive side, so that the clock at each data flip-flop is phase-matched to the received clock. In that type of application, a special form of a PLL called a [[delay-locked loop]] (DLL) is frequently used.<ref>{{cite web |url         = http://www-vlsi.stanford.edu/papers/mh_micro_98.pdf |author1     = M Horowitz |author2     = C. Yang |author3     = S. Sidiropoulos |title       = High-speed electrical signaling: overview and limitations |publisher   = IEEE Micro |date        = 1998-01-01 |url-status     = dead |archive-url  = https://web.archive.org/web/20060221015031/http://www-vlsi.stanford.edu/papers/mh_micro_98.pdf |archive-date = 2006-02-21}}</ref>

===Clock generation===
Many electronic systems include processors of various sorts that operate at hundreds of megahertz to gigahertz, well above the practical frequencies of [[crystal oscillators]]. Typically, the clocks supplied to these processors come from clock generator PLLs, which multiply a lower-frequency reference clock (usually 50 or 100&nbsp;MHz) up to the operating frequency of the processor. The multiplication factor can be quite large in cases where the operating frequency is multiple gigahertz and the reference crystal is just tens or hundreds of megahertz.

===Spread spectrum===
All electronic systems emit some unwanted radio frequency energy. Various regulatory agencies (such as the [[Federal Communications Commission|FCC]] in the United States) put limits on the emitted energy and any interference caused by it. The emitted noise generally appears at sharp spectral peaks (usually at the operating frequency of the device, and a few harmonics). A system designer can use a spread-spectrum PLL to reduce interference with high-Q receivers by spreading the energy over a larger portion of the spectrum. For example, by changing the operating frequency up and down by a small amount (about 1%), a device running at hundreds of megahertz can spread its interference evenly over a few megahertz of spectrum, which drastically reduces the amount of noise seen on broadcast [[FM broadcasting|FM radio]] channels, which have a bandwidth of several tens of kilohertz.

===Clock distribution===
[[File:PLL usage.svg|center]]
Typically, the reference clock enters the chip and drives a phase locked loop (PLL), which then drives the system's clock distribution. The clock distribution is usually balanced so that the clock arrives at every endpoint simultaneously. One of those endpoints is the PLL's feedback input. The function of the PLL is to compare the distributed clock to the incoming reference clock, and vary the phase and frequency of its output until the reference and feedback clocks are phase and frequency matched.

PLLs are ubiquitous—they tune clocks in systems several feet across, as well as clocks in small portions of individual chips. Sometimes the reference clock may not actually be a pure clock at all, but rather a data stream with enough transitions that the PLL is able to recover a regular clock from that stream. Sometimes the reference clock is the same frequency as the clock driven through the clock distribution, other times the distributed clock may be some rational multiple of the reference.

===AM detection===
A PLL may be used to synchronously demodulate amplitude modulated (AM) signals. The PLL recovers the phase and frequency of the incoming AM signal's carrier. The recovered phase at the VCO differs from the carrier's by 90°, so it is shifted in phase to match, and then fed to a multiplier. The output of the multiplier contains both the sum and the difference frequency signals, and the demodulated output is obtained by [[low-pass filtering]]. Since the PLL responds only to the carrier frequencies which are very close to the VCO output, a PLL AM detector exhibits a high degree of selectivity and noise immunity which is not possible with conventional peak type AM demodulators. However, the loop may lose lock where AM signals have 100% modulation depth.<ref>{{citation |first=Robert |last=Dixon |title=Radio Receiver Design |publisher=CRC Press |date=1998 |isbn=0824701615 |page=215}}</ref>

===Jitter and noise reduction===
One desirable property of all PLLs is that the reference and feedback clock edges be brought into very close alignment. The average difference in time between the phases of the two signals when the PLL has achieved lock is called the '''static phase offset''' (also called the '''steady-state phase error'''). The variance between these phases is called '''tracking [[jitter]]'''. Ideally, the static phase offset should be zero, and the tracking jitter should be as low as possible.{{Dubious|date=September 2010}}<!-- If phase variance between input and output is 0, no jitter attenuation is possible. -->

[[Phase noise]] is another type of jitter observed in PLLs, and is caused by the oscillator itself and by elements used in the oscillator's frequency control circuit. Some technologies are known to perform better than others in this regard. The best digital PLLs are constructed with emitter-coupled logic ([[Emitter coupled logic|ECL]]) elements, at the expense of high power consumption. To keep phase noise low in PLL circuits, it is best to avoid saturating logic families such as transistor-transistor logic ([[transistor-transistor logic|TTL]]) or [[CMOS]].<ref>{{Cite book|last1=Basab Bijoy Purkayastha|title=A Digital Phase Locked Loop based Signal and Symbol Recovery System for Wireless Channel|last2=Kandarpa Kumar Sarma|publisher=Springer (India) Pvt. Ltd. (Part of Springer Science+Business Media)|year=2015|isbn=978-81-322-2040-4|location=India|pages=5}}</ref>

Another desirable property of all PLLs is that the phase and frequency of the generated clock be unaffected by rapid changes in the voltages of the power and ground supply lines, as well as the voltage of the substrate on which the PLL circuits are fabricated. This is called substrate and [[Power supply rejection ratio|supply noise rejection]]. The higher the noise rejection, the better.

To further improve the phase noise of the output, an [[injection locked oscillator]] can be employed following the VCO in the PLL.

===Frequency synthesis===
In digital wireless communication systems (GSM, CDMA etc.), PLLs are used to provide the local oscillator up-conversion during transmission and [[Digital down converter|down-conversion]] during reception. In most cellular handsets this function has been largely integrated into a single integrated circuit to reduce the cost and size of the handset. However, due to the high performance required of base station terminals, the transmission and reception circuits are built with discrete components to achieve the levels of performance required. GSM local oscillator modules are typically built with a [[frequency synthesizer]] integrated circuit and discrete resonator VCOs.{{Citation needed|date=May 2010}}

===Phase angle reference===
[[Grid-tie inverter]]s based on voltage source inverters source or sink real power into the AC electric grid as a function of the phase angle of the voltage they generate relative to the grid's voltage phase angle, which is measured using a PLL. In [[photovoltaic]] applications, the more the sine wave produced leads the grid voltage wave, the more power is injected into the grid. For battery applications, the more the sine wave produced lags the grid voltage wave, the more the battery charges from the grid, and the more the sine wave produced leads the grid voltage wave, the more the battery discharges into the grid.{{Citation needed|date=December 2023|reason=Citation would be appreciated. Would help readers know where to look for more information on the subject.}}