Editing PowerPC (section)

=== Endian modes ===<!-- This section is linked from [[PowerPC]] -->

Most PowerPC chips switch endianness via a bit in the MSR ([[machine state register]]), with a second bit provided to allow the OS to run with a different endianness. Accesses to the "[[inverted page table]]" (a hash table that functions as a [[Translation lookaside buffer|TLB]] with off-chip storage) are always done in big-endian mode. The processor starts in big-endian mode.

In little-endian mode, the three lowest-order bits of the effective address are [[Exclusive or|exclusive-ORed]] with a three bit value selected by the length of the operand. This is enough to appear fully little-endian to normal software. An operating system will see a warped view of the world when it accesses external chips such as video and network hardware. Fixing this warped view requires that the motherboard perform an unconditional 64-bit byte swap on all data entering or leaving the processor. Endianness thus becomes a property of the motherboard. An OS that operates in little-endian mode on a big-endian motherboard must both swap bytes and undo the exclusive-OR when accessing little-endian chips.

[[AltiVec]] operations, despite being 128-bit, are treated as if they were 64-bit. This allows for compatibility with little-endian motherboards that were designed prior to AltiVec.

An interesting side effect of this implementation is that a program can store a 64-bit value (the longest operand format) to memory while in one endian mode, switch modes, and read back the same 64-bit value without seeing a change of byte order. This will not be the case if the motherboard is switched at the same time.

[[Mercury Systems]] and [[Matrox]] ran the PowerPC in little-endian mode. This was done so that PowerPC devices serving as co-processors on PCI boards could share data structures with host computers based on [[x86]]. Both PCI and x86 are little-endian. OS/2 and Windows NT for PowerPC ran the processor in little-endian mode while Solaris, AIX and Linux ran in big endian.<ref>{{cite web| url=http://www.os2museum.com/wp/os2-for-powerpc-tidbits/ |title=OS/2 for PowerPC Tidbits |archive-url=https://web.archive.org/web/20160131121239/http://www.os2museum.com/wp/os2-for-powerpc-tidbits/ |archive-date=January 31, 2016 |date=16 November 2012 |first=Michal |last=Necasek |website=OS/2 Museum}}</ref>

Some of IBM's embedded PowerPC chips use a per-page [[endianness]] bit. None of the previous applies to them.