Editing Power management (section)

===Power gating techniques===
Much research has been done on the dynamic power reduction with the use of DVFS techniques. However, as technology continues to shrink, leakage power will become a dominant factor.<ref>"[https://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=782564 Design challenges of technology scaling]", Borkar, S., IEEE Micro  (Volume:19,  Issue: 4 ), 1999.</ref> [[Power gating]] is a commonly used circuit technique to remove leakage by turning off the supply voltage of unused circuits. Power gating incurs energy overhead; therefore, unused circuits need to remain idle long enough to compensate this overheads.
A novel micro-architectural technique<ref>"[https://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6176483 Run-time power-gating in caches of GPUs for leakage energy savings]", Yue Wang et al., Design, Automation & Test in Europe Conference & Exhibition (DATE), 2012</ref> for run-time power-gating caches of GPUs saves leakage energy. Based on experiments on 16 different GPU workloads, the average energy savings achieved by the proposed technique is 54%.
Shaders are the most power hungry component of a GPU, a predictive shader shut down power gating technique<ref>"[https://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=4758617 A Predictive Shutdown Technique for GPU Shader Processors]", Po-Han Wang et al., Computer Architecture Letters  (Volume: 8,  Issue: 1 ), 2009</ref> achieves up to 46% leakage reduction on shader processors.
The Predictive Shader Shutdown technique exploits workload variation across frames to eliminate leakage in shader clusters. Another technique called Deferred Geometry Pipeline seeks to minimize leakage in [[fixed function units|fixed-function geometry units]] by utilizing an imbalance between geometry and fragment computation across batches which removes up to 57% of the leakage in the fixed-function geometry units. A simple time-out power gating method can be applied to non-shader execution units which eliminates 83.3% of the leakage in non-shader execution units on average.
All the three techniques stated above incur negligible performance degradation, less than 1%.<ref>"[http://dl.acm.org/citation.cfm?id=2019612 Power gating strategies on GPUs]", Po-Han Wang et al., ACM Transactions on Architecture and Code Optimization (TACO) Volume 8 Issue 3, 2011</ref>