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====Examples of gate equivalent technique==== * '''Class-independent power modeling:''' It is a technique which tries to estimate chip area, speed, and power dissipation based on information about the complexity of the design in terms of gate equivalents. The functionality is divided among different blocks but no distinction is made about the functionality of the blocks i.e. it is basically class independent. This is the technique used by the ''chip estimation system'' (CES). ::'''Steps:''' ::# Identify the functional blocks such as counters, decoders, multipliers, memories, etc. ::# Assign a complexity in terms of gate equivalents. The number of GE’s for each unit type are either taken directly as an input from the user or are fed from a library. <div style="text-align: center"> :<math>\displaystyle P = \sum_{i \in \text{fns}} \textit{GE}_i (E_\text{typ} + C_L^i V_\text{dd}^2) f A_\text{int}^i</math> </div> ::Where E<sub>typ</sub> is the assumed average dissipated energy by a gate equivalent, when active. The activity factor, A<sub>int</sub>, denotes the average percentage of gates switching per clock cycle and is allowed to vary from function to function. The capacitive load, C<sub>L</sub>, is a combination of fan-out loading as well as wiring. An estimate of the average wire length can be used to calculate the wiring capacitance. This is provided by the user and cross-checked by using a derivative of [[Rent's rule|Rent’s rule]]. ::'''Assumptions:''' ::# A single reference gate is taken as the basis for all the power estimates not taking into consideration different circuit styles, clocking strategies, or layout techniques. ::# The percentage of gates switching per clock cycle denoted by activity factors are assumed to be fixed regardless of the input patterns. ::# Typical gate switching energy is characterized by completely random uniform [[white noise]] (UWN) distribution of the input data. This implies that the power estimation is same regardless of the circuit being idle or at maximum load as this UWN model ignores how different input distributions affect the power consumption of gates and modules.<ref>[http://delivery.acm.org/10.1145/250000/244548/p158-raghunathan.pdf?ip=103.27.8.42&id=244548&acc=ACTIVE%20SERVICE&key=045416EF4DDA69D9%2EF8E7F338DF557316%2E4D4702B0C3E38B35%2E4D4702B0C3E38B35&CFID=504808115&CFTOKEN=79046804&__acm__=1429710434_0d9c0bce018bcd071c079ecb15be69e8 "Register-Transfer Level Estimation Techniques for Switching Activity and Power Consumption"]</ref> * '''Class-dependent power modeling:''' This approach is slightly better than the previous approach as it takes into account customized estimation techniques to the different types of functional blocks thus trying to increase the modelling accuracy which wasn’t the case in the previous technique such as logic, memory, interconnect, and clock hence the name. The power estimation is done in a very similar manner to the independent case. The basic switching energy is based on a three-input AND gate and is calculated from technology parameters e.g. gate width, tox, and metal width provided by the user. <div style="text-align: center"> :<math>P_\text{bitlines} = \dfrac{N_\text{col}}{2} \cdot (L_\text{col} C_\text{wire} + N_\text{row} C_\text{cell}) V_\text{dd} V_\text{swing}</math> </div> ::Where C<sub>wire</sub> denotes the bit line wiring capacitance per unit length and C<sub>cell</sub> denotes the loading due to a single cell hanging off the bit line. The clock capacitance is based on the assumption of an [[H-tree]] distribution network. Activity is modelled using a UWN model. As can be seen by the equation the power consumption of each components is related to the number of columns (N<sub>col</sub>) and rows (N<sub>row</sub>) in the memory array. ::'''Disadvantages:''' ::# The circuit activities are not modeled accurately as an overall activity factor is assumed for the entire chip which is also not trustable as provided by the user. As a matter of fact activity factors will vary throughout the chip hence this is not very accurate and prone to error. This leads to the problem that even if the model gives a correct estimate for the total power consumption by the chip, the module wise power distribution is fairly inaccurate. ::#The chosen activity factor gives the correct total power, but the breakdown of power into logic, clock, memory, etc. is less accurate. Therefore this tool is not much different or improved in comparison with CES.
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