Editing Register allocation (section)

==== Principle ====
The main phases in a Chaitin-style graph-coloring register allocator are:{{sfn|Briggs|Cooper|Torczon|1992|p=316}}
[[File:Chaitin et al.'s iteravite graph coloring based register allocator.png|thumb|700px|Chaitin et al.'s iterative graph coloring based register allocator]]
# '''Renumber''': discover live range information in the source program.
# '''Build''': build the interference graph.
# '''Coalesce''': merge the live ranges of non-interfering variables related by copy instructions.
# '''Spill cost''': compute the spill cost of each variable. This assesses the impact of mapping a variable to memory on the speed of the final program.
# '''Simplify''': construct an ordering of the nodes in the inferences graph
# '''Spill Code''': insert spill instructions, i.e. loads and stores to commute values between registers and memory.
# '''Select''': assign a register to each variable.