Editing SPARC (section)

====Loads and stores====
Load and store instructions have a three-operand format, in that they have two operands representing values for the address and one operand for the register to read or write to. The address is created by adding the two address operands to produce an address. The second address operand may be a constant or a register. Loads take the value at the address and place it in the register specified by the third operand, whereas stores take the value in the register specified by the first operand and place it at the address. To make this more obvious, the [[assembler language]] indicates address operands using square brackets with a plus sign separating the operands, instead of using a comma-separated list. Examples:<ref name=ncsu/>

 ld [%L1+%L2],%L3  !load the 32-bit value at address %L1+%L2 and put the value into %L3
 ld [%L1+8],%L2    !load the value at %L1+8 into %L2
 ld [%L1],%L2      !as above, but no offset, which is the same as +%G0
 st %L1,[%I2]      !store the value in %L1 into the location stored in %I2
 st %G0,[%I1+8]    !clear the memory at %I1+8

Due to the widespread use of non-32-bit data, such as 16-bit or 8-bit integral data or 8-bit bytes in strings, there are instructions that load and store 16-bit half-words and 8-bit bytes, as well as instructions that load 32-bit words. During a load, those instructions will read only the byte or half-word at the indicated location and then either fill the rest of the target register with zeros (unsigned load) or with the value of the uppermost bit of the byte or half-word (signed load). During a store, those instructions discard the upper bits in the register and store only the lower bits. There are also instructions for loading double-precision values used for [[floating-point arithmetic]], reading or writing eight bytes from the indicated register and the "next" one, so if the destination of a load is L1, L1 and L2 will be set. The complete list of load and store instructions for the general-purpose registers in 32-bit SPARC is {{code|LD}}, {{code|ST}}, {{code|LDUB}} (unsigned byte), {{code|LDSB}} (signed byte), {{code|LDUH}} (unsigned half-word), {{code|LDSH}} (signed half-word), {{code|LDD}} (load double), {{code|STB}} (store byte), {{code|STH}} (store half-word), {{code|STD}} (store double).<ref name=ncsu/>

In SPARC V9, registers are 64-bit, and the {{code|LD}} instruction, renamed {{code|LDUW}}, clears the upper 32 bits in the register and loads the 32-bit value into the lower 32 bits, and the {{code|ST}} instruction, renamed {{code|STW}}, discards the upper 32 bits of the register and stores only the lower 32 bits.  The new {{code|LDSW}} instruction sets the upper bits in the register to the value of the uppermost bit of the word and loads the 32-bit value into the lower bits. The new {{code|LDX}} instruction loads a 64-bit value into the register, and the {{code|STX}} instruction stores all 64 bits of the register.

The {{code|LDF}}, {{code|LDDF}}, and {{code|LDQF}} instructions load a single-precision, double-precision, or quad-precision value from memory into a floating-point register; the {{code|STF}}, {{code|STDF}}, and {{code|STQF}} instructions store a single-precision, double-precision, or quad-precision floating-point register into memory.

The [[memory barrier]] instruction, MEMBAR, serves two interrelated purposes: it articulates order constraints among memory references and facilitates explicit control over the completion of memory references. For example, all effects of the stores that appear prior to the MEMBAR instruction must be made visible to all processors before any loads following the MEMBAR can be executed.<ref>{{Cite web |url=https://www.fujitsu.com/hk/imagesgig5/sparc64ixfx-extensions.pdf#page=103 |title=SPARC64 IXfx Extensions Fujitsu Limited Ver 12, 2 Dec. 2013 |pages=103–104 |accessdate=2023-12-17}}</ref>