Editing Streaming SIMD Extensions (section)

== Later versions ==
* [[SSE2]], Willamette New Instructions (WNI), introduced with the [[Pentium 4]], is a major enhancement to SSE. SSE2 adds two major features: [[double-precision]] (64-bit) floating-point for all SSE operations, and MMX integer operations on 128-bit XMM registers. In the original SSE instruction set, conversion to and from integers placed the integer data in the 64-bit MMX registers. SSE2 enables the programmer to perform SIMD math on any data type (from 8-bit integer to 64-bit float) entirely with the XMM vector-register file, without the need to use the legacy MMX or FPU registers. It offers an [[orthogonal instruction set|orthogonal set of instructions]] for dealing with common data types.
* [[SSE3]], also called Prescott New Instructions (PNI), is an incremental upgrade to SSE2, adding a handful of DSP-oriented mathematics instructions and some process (thread) management instructions. It also allowed addition or multiplication of two numbers that are stored in the same register, which wasn't possible in SSE2 and earlier. This capability, known as horizontal in Intel terminology, was the major addition to the SSE3 instruction set. AMD's [[3DNow!]] extension could do the latter too.
* [[SSSE3]], Merom New Instructions (MNI), is an upgrade to SSE3, adding 16 new instructions which include permuting the bytes in a word, multiplying 16-bit fixed-point numbers with correct rounding, and within-word accumulate instructions. SSSE3 is often mistaken for SSE4 as this term was used during the development of the Core [[microarchitecture]].
* [[SSE4]], Penryn New Instructions (PNI), is another major enhancement, adding a [[dot product]] instruction, additional integer instructions, a [[SSE4#POPCNT and LZCNT|<syntaxhighlight lang="asm" inline>popcnt</syntaxhighlight> instruction]] ([[Hamming weight|Population count]]: count number of bits set to 1, used extensively e.g. in [[cryptography]]), and more.
* [[XOP instruction set|XOP]], [[FMA instruction set|FMA4]] and [[CVT16 instruction set|CVT16]] are new iterations announced by [[AMD]] in August 2007<ref name=":0">{{cite web
| url=https://www.theregister.co.uk/2007/08/30/amd_sse5/
| title=AMD plots single thread boost with x86 extensions
| website=[[The Register]]
| first=Ashlee
| last=Vance
| author-link=Ashlee Vance
| date=August 3, 2007
| access-date=August 24, 2017
| archive-date=April 27, 2011
| archive-url=https://web.archive.org/web/20110427144442/http://www.theregister.co.uk/2007/08/30/amd_sse5/
| url-status=live
}}</ref><ref>{{cite web
| url=http://developer.amd.com/wordpress/media/2012/10/AMD64_128_Bit_SSE5_Instrs.pdf
| title=AMD64 Technology: 128-Bit SSE5 Instruction Set
| date=August 2007
| publisher=[[AMD]]
| access-date=August 24, 2017
| archive-date=August 25, 2017
| archive-url=https://web.archive.org/web/20170825103549/http://developer.amd.com/wordpress/media/2012/10/AMD64_128_Bit_SSE5_Instrs.pdf
| url-status=live
}}</ref> and revised in May 2009.<ref>{{cite web
| url=https://support.amd.com/TechDocs/43479.pdf
| title=AMD64 Technology AMD64 Architecture Programmer's Manual Volume 6: 128-Bit and 256-Bit XOP and FMA4 Instructions
| date=November 2009
| publisher=AMD
| access-date=August 24, 2017
| archive-date=January 31, 2017
| archive-url=https://web.archive.org/web/20170131212831/http://support.amd.com/TechDocs/43479.pdf
| url-status=live
}}</ref>
* [[Advanced Vector Extensions]] (AVX), Gesher New Instructions (GNI), is an advanced version of SSE announced by Intel featuring a widened data path from 128 bits to 256 bits and 3-operand instructions (up from 2). Intel released processors in early 2011 with AVX support.<ref>{{cite web
| last=Girkar
| first=Milind
| url=https://software.intel.com/en-us/isa-extensions/intel-avx
| title=Intel® Advanced Vector Extensions (Intel® AVX)
| publisher=[[Intel]]
| date=October 1, 2013
| access-date=August 24, 2017
| archive-date=August 25, 2017
| archive-url=https://web.archive.org/web/20170825102628/https://software.intel.com/en-us/isa-extensions/intel-avx
| url-status=live
}}</ref>
* [[Advanced Vector Extensions#Advanced Vector Extensions 2|AVX2]] is an expansion of the AVX instruction set.
* [[AVX-512]] (3.1 and 3.2) are 512-bit extensions to the 256-bit Advanced Vector Extensions SIMD instructions for x86 instruction set architecture.