Editing Universal asynchronous receiver-transmitter (section)

== Models ==
A dual UART, or ''DUART'', combines two UARTs into a single chip. Similarly, a quadruple UART or ''QUART'', combines four UARTs into one package, such as the NXP 28L194. An octal UART or ''OCTART'' combines eight UARTs into one package, such as the [[Exar Corporation|Exar]] XR16L788 or the NXP SCC2698.
{| class="wikitable"
|-
! Model !! Description
|-
| WD1402A
| The first single-chip UART on general sale. Introduced about 1971. Compatible chips included the Fairchild TR1402A and the General Instruments AY-5-1013.<ref>''[http://retrocmp.com/how-tos/interfacing-to-a-pdp-1105/143-interfacing-with-a-pdp-1105-the-uart Interfacing with a PDP-11/05: the UART]'', blinkenbone.com, accessed 2015-08-19</ref>
|-
| Exar XR21V1410
|
|-
| Intersil 6402
|
|-
| CDP 1854 (RCA, now Intersil)
|
|-
| Zilog Z8440
| [[Universal synchronous and asynchronous receiver-transmitter]] (USART). {{nowrap|2000 kbit/s}}. Async, <!--IBM-->[[Binary Synchronous Communications|Bisync]], [[Synchronous Data Link Control|SDLC]], [[High-Level Data Link Control|HDLC]], <!--CCITT-->[[X.25]]. [[Cyclic redundancy check|CRC]]. 4-byte RX buffer. 2-byte TX buffer. Provides signals needed by a third party [[Direct memory access|DMA]] controller to perform DMA transfers.<ref name="zilog_com-ps0183">{{cite web|title=Zilog Product specification Z8440/1/2/4, Z84C40/1/2/3/4. Serial input/output controller|url=http://www.zilog.com/docs/z80/ps0183.pdf}} 090529 zilog.com</ref>
|-
| [[Zilog SCC|Z8530/Z85C30]]
| This USART has a 3-byte receive buffer and a 1-byte transmit buffer. It has hardware to accelerate the processing of HDLC and SDLC. The CMOS version (Z85C30) provides signals to allow a third party DMA controller to perform DMA transfers. It can do asynchronous, byte level synchronous, and bit level synchronous communications.<ref>{{cite web|url=http://www.zilog.com/docs/serial/PS0117.pdf|title=Zilog Document Download|website=www.zilog.com|access-date=22 March 2018}}</ref>
|-
| [[8250 UART|8250]]
|rowspan="6"| Obsolete with 1-byte buffers. These UARTs' maximum standard serial port speed is 9600&nbsp;bits per second if the operating system has a 1 millisecond [[interrupt latency]]. 8250 UARTs were used in the [[IBM 5150|IBM PC 5150]] and IBM PC/XT, while the 16450 UART were used in [[IBM PC/AT]]-series computers. The 8251 has USART capability.
|-
| [[Intel 8251|8251]]
|-
| Motorola 6850
|-
| [[MOS Technology 6551|6551]]
|-
| Rockwell 65C52
|-
| 16450
|-
| 82510
| This UART allows asynchronous operation up to {{nowrap|288 kbit/s}}, with two independent four-byte FIFOs. It was produced by Intel at least from 1993 to 1996, and Innovastic Semiconductor has a 2011 Data Sheet for IA82510.
|-
| [[16550 UART|16550]]
| This UART was introduced by Startech Semiconductor which is now owned by [[Exar Corporation]] and is not related to Startech.com. Early versions have a broken FIFO buffer and therefore cannot safely run any faster than the 16450 UART.<ref>{{cite web |url=http://www.mail-archive.com/linux-serial@vger.rutgers.edu/msg00065.html |title=Re: Serial communication with the 16650 |last1=T'so |first1=Theodore Y. |date=January 23, 1999 |website=The Mail Archive |access-date=June 2, 2013}}</ref> Versions of this UART that were not broken have 32-character FIFO buffers and could function at standard serial port speeds up to {{nowrap|230.4 kbit/s}} if the operating system has a 1 millisecond interrupt latency. Current versions of this UART by Exar claim to be able to handle up to {{nowrap|1.5 Mbit/s}}. This UART introduces the Auto-RTS and Auto-CTS features in which the RTS# signal is controlled by the UART to signal the external device to stop transmitting when the UART's buffer is full to or beyond a user-set trigger point and to stop transmitting to the device when the device drives the CTS# signal high (logic 0).
|-
| [[16550 UART|16550A]]
|rowspan="2"| This UART has 16-byte FIFO buffers. Its receive interrupt trigger levels can be set to 1, 4, 8, or 14 characters. Its maximum standard serial port speed if the operating system has a 1 millisecond interrupt latency is {{nowrap|128 kbit/s}}. Systems with lower interrupt latencies or with DMA controllers could handle higher baud rates. This chip can provide signals that are needed to allow a DMA controller to perform DMA transfers to and from the UART if the DMA mode this UART introduces is enabled.<ref name="cs_utk_edu-mswin_serial_faq">{{Cite FTP |title=FAQ: The 16550A UART & TurboCom drivers 1994|url=ftp://ftp.cs.utk.edu/pub/shuford/terminal/mswin_serial_faq.txt|server=FTP server|url-status=dead|access-date=January 16, 2016}}</ref> It was introduced by National Semiconductor, which has been sold to Texas Instruments. National Semiconductor claimed that this UART could run at up to {{nowrap|1.5 Mbit/s}}.
|-
| 16C552
|-
| 16750 || 64-byte buffers. This UART can handle a maximum standard serial port speed of {{nowrap|460.8 kbit/s}} if the maximum interrupt latency is 1&nbsp;millisecond. This UART was introduced by Texas Instruments. TI claims that early models can run up to {{nowrap|1 Mbit/s}}, and later models in this series can run up to {{nowrap|3 Mbit/s}}.
|-
| 16850
|rowspan="2"| 128-byte buffers. This UART can handle a maximum standard serial port speed of {{nowrap|921.6 kbit/s}} if the maximum interrupt latency is 1&nbsp;millisecond. This UART was introduced by Exar Corporation. Exar claims that early versions can run up to {{nowrap|2 Mbit/s}}, and later versions can run up to {{nowrap|2.25 Mbit/s}} depending on the date of manufacture.
|-
| 16C850
|-
| 16950
| rowspan="2"|128-byte buffers. This UART can handle a maximum standard serial port speed of {{nowrap|921.6 kbit/s}} if the maximum interrupt latency is 1 millisecond. This UART supports 9-bit characters in addition to the 5- to 8-bit characters that other UARTs support. This was introduced by Oxford Semiconductor, which is now owned by PLX Technology. Oxford/PLX claims that this UART can run up to {{nowrap|15 Mbit/s}}. PCI Express variants by Oxford/PLX are integrated with a first party bus mastering PCIe DMA controller. This DMA controller uses the UART's DMA mode signals that were defined for the 16550. The DMA controller requires the CPU to set up each transaction and poll a status register after the transaction is started to determine if the transaction is done. Each DMA transaction can transfer between 1 and 128 bytes between a memory buffer and the UART. PCI Express variants can also allow the CPU to transfer data between itself and the UART with 8-, 16-, or 32-bit transfers when using programmed I/O.
|-
| 16C950
|-
| 16954
| rowspan="2"|Quad-port version of the 16950/16C950. 128-byte buffers. This UART can handle a maximum standard serial port speed of {{nowrap|921.6 kbit/s}} if the maximum interrupt latency is 1 millisecond. This UART supports 9-bit characters in addition to the 5–8&nbsp;bit characters that other UARTs support. This was introduced by Oxford Semiconductor, which is now owned by PLX Technology. Oxford/PLX claims that this UART can run up to {{nowrap|15 Mbit/s}}. PCI Express variants by Oxford/PLX are integrated with a first party bus mastering PCIe DMA controller. This DMA controller is controlled by the UART's DMA mode signals that were defined for the 16550. The DMA controller requires the CPU to set up each transaction and poll a status register after the transaction is started to determine if the transaction is done. Each DMA transaction can transfer between 1 and 128 bytes between a memory buffer and the UART. PCI Express variants can also allow the CPU to transfer data between itself and the UART with 8-, 16-, or 32-bit transfers when using programmed I/O.
|-
| 16C954
|-
| 16C1550/16C1551||UART with 16-byte FIFO buffers. Up to {{nowrap|1.5 Mbit/s}}. The ST16C155X is not compatible with the industry standard 16550 and will not work with the standard serial port driver in Microsoft Windows.
|-
| 16C2450||Dual UART with 1-byte FIFO buffers.
|-
| 16C2550||Dual UART with 16-byte FIFO buffers. Pin-to-pin and functional compatible to 16C2450. Software compatible with INS8250 and NS16C550.
|-
| SCC2691
|rowspan="2"|Currently produced by [[NXP]], the 2691<ref name="nxp_SCC2691" /> is a single channel UART that also includes a programmable counter/timer. The 2691 has a single-byte transmitter holding register and a 4-byte receive [[FIFO (computing and electronics)|FIFO]]. Maximum standard speed of the 2692 is {{nowrap|115.2 kbit/s}}.

The 28L91 is an upwardly compatible version of the 2691, featuring selectable 8- or 16-byte transmitter and receiver FIFOs, improved support for extended data rates, and faster bus timing characteristics, making the device more suitable for use with high performance microprocessors.

Both the 2691 and 28L91 may also be operated in [[RS-422|TIA-422]] and [[RS-485|TIA-485]] modes, and may also be programmed to support non-standard data rates. The devices are produced in PDIP-40, PLCC-44 and 44 pin QFP packages, and are readily adaptable to both [[Motorola 68000 family|Motorola]] and [[x86|Intel]] buses. They have also been successfully adapted to the [[65C02]] and [[65C816]] buses. The 28L91 will operate on 3.3 or 5 volts.
|-
| SCC28L91
|-
| SCC2692
| rowspan="3"|Currently produced by NXP, these devices are dual UARTs (DUART), consisting of two communications channels, associated control registers and one counter/timer. Each communication channel is independently programmable and supports independent transmit and receive data rates.

The 2692 has a single-byte transmitter holding register and a 4-byte receiver [[FIFO (computing and electronics)|FIFO]] for each channel. Maximum standard speed of both of the 2692's channels is {{nowrap|115.2 kbit/s}}.

The 26C92 is an upwardly compatible version of the 2692, with 8-byte transmitter and receiver FIFOs for improved performance during continuous bi-directional asynchronous transmission (CBAT) on both channels at the maximum standard speed of {{nowrap|230.4 kbit/s}}. The letter '''C''' in the 26C92 part number has nothing to do with the fabrication process; all NXP UARTs are [[CMOS]] devices.

The 28L92 is an upwardly compatible version of the 26C92, featuring selectable 8- or 16-byte transmitter and receiver FIFOs, improved support for extended data rates, and faster bus timing characteristics, making the device more suitable for use with high performance microprocessors.

The 2692, 26C92 and 28L92 may be operated in TIA-422 and TIA-485 modes, and may also be programmed to support non-standard data rates. The devices are produced in PDIP-40, PLCC-44 and 44 pin QFP packages, and are readily adaptable to both Motorola and Intel buses. They have also been successfully adapted to the 65C02 and 65C816 buses. The 28L92 will operate on 3.3 or 5 volts.
|-
| SC26C92
|-
| SC28L92
|-
| SCC28C94||Currently produced by NXP, the 28C94 quadruple UART (QUART) is functionally similar to a pair of SCC26C92 DUARTs mounted in a common package, with the addition of an arbitrated interrupt system for efficient processing during periods of intense channel activity. Some additional signals are present to support the interrupt management features and the auxiliary input/output pins are arranged differently than those of the 26C92. Otherwise, the programming model for the 28C94 is similar to that of the 26C92, requiring only minor code changes to fully utilize all features. The 28C94 supports a maximum standard speed of {{nowrap|230.4 kbit/s}}, is available in a PLCC-52 package, and is readily adaptable to both Motorola and Intel buses. It has also been successfully adapted to the 65C816 bus.
|-
| SCC2698B||Currently produced by NXP, the 2698 octal UART (OCTART) is essentially four SCC2692 DUARTs in a single package. Specifications are the same as the SCC2692 (not the SCC26C92). Due to the lack of transmitter FIFOs and the small size of the receiver FIFOs, the 2698 can cause an interrupt "storm" if all channels are simultaneously engaged in continuous bi-directional communication. The device is produced in PDIP-64 and PLCC-84 packages, and is readily adaptable to both Motorola and Intel buses. The 2698 has also been successfully adapted to the 65C02 and 65C816 buses.
|-
| SCC28L198||Currently produced by NXP, the 28L198 OCTART is essentially an upscaled enhancement of the SCC28C94 QUART described above, with eight independent communications channels, as well as an arbitrated interrupt system for efficient processing during periods of intense channel activity. The 28L198 supports a maximum standard speed of {{nowrap|460.8 kbit/s}}, is available in PLCC-84 and LQFP-100 packages, and is readily adaptable to both Motorola and Intel buses. The 28L198 will operate on 3.3 or 5 volts.
|-
| [[Zilog SCC|Z85230]] || Synchronous/Asynchronous modes (USART),<ref>{{cite web |author1=Zilog |title=SCC/ESCC User Manual UM010901-0601 |url=http://data.leocom.kr/datasheets/207906_91825.pdf |website=leocom.kr |access-date=13 May 2023}}</ref> 2 ports. Provides signals needed by a third party DMA controller needed to perform DMA transfers. 4-byte buffer to send, 8-byte buffer to receive per channel. SDLC/HDLC modes. {{nowrap|5 Mbit/s}} in synchronous mode.
|-
| {{nowrap|Hayes ESP}} || {{nowrap|1 KB}} buffers, {{nowrap|921.6 kbit/s}}, 8-ports.<ref>[http://bill.herrin.us/freebies/hayes-esp8/ bill.herrin.us - Hayes ESP 8-port Enhanced Serial Port Manual], 2004-03-02</ref>
|-
| Exar XR17V352, XR17V354 and XR17V358 || Dual, Quad and Octal PCI Express UARTs with 16550 compatible register Set, 256-byte TX and RX FIFOs, Programmable TX and RX Trigger Levels, TX/RX FIFO Level Counters, Fractional baud rate generator, Automatic RTS/CTS or DTR/DSR hardware flow control with programmable hysteresis, Automatic Xon/Xoff software flow control, RS-485 half duplex direction control output with programmable turn-around delay, Multi-drop with Auto Address Detection, Infrared (IrDA 1.1) data encoder/decoder. They are specified up to {{nowrap|25 Mbit/s}}. DataSheets are dated from 2012.
|-
| Exar XR17D152, XR17D154 and XR17D158 || Dual, Quad and Octal PCI bus UARTs with 16C550 Compatible 5G Register Set, 64-byte Transmit and Receive FIFOs, Transmit and Receive FIFO Level Counters, Programmable TX and RX FIFO Trigger Level, Automatic RTS/CTS or DTR/DSR Flow Control, Automatic Xon/Xoff Software Flow Control, RS485 HDX Control Output with Selectable Turn-around Delay, Infrared (IrDA 1.0) Data Encoder/Decoder, Programmable Data Rate with Prescaler, Up to {{nowrap|6.25 Mbit/s}} Serial Data Rate. DataSheets are dated from 2004 and 2005.
|-
| Exar XR17C152, XR17C154 and XR17C158 || Dual, Quad and Octal 5&nbsp;V PCI bus UARTs with 16C550 Compatible Registers, 64-byte Transmit and Receive FIFOs, Transmit and Receive FIFO Level Counters, Automatic RTS/CTS or DTR/DSR Flow Control, Automatic Xon/Xoff Software Flow Control, RS485 Half-duplex Control with Selectable Delay, Infrared (IrDA&nbsp;1.0) Data Encoder/Decoder, Programmable Data Rate with Prescaler, Up to {{nowrap|6.25 Mbit/s}} Serial Data Rate. DataSheets are dated from 2004 and 2005.
|-
| Exar XR17V252, XR17V254 and XR17V258 || Dual, Quad and Octal 66&nbsp;MHz PCI bus UARTs with Power Management Support, 16C550 compatible register set, 64-byte TX and RX FIFOs with level counters and programmable trigger levels, Fractional baud rate generator, Automatic RTS/CTS or DTR/DSR hardware flow control with programmable hysteresis, Automatic Xon/Xoff software flow control, RS-485 half duplex direction control output with selectable turn-around delay, Infrared (IrDA&nbsp;1.0) data encoder/decoder, Programmable data rate with prescaler. DataSheets are dated from 2008 and 2010.
|}