Editing Verilog (section)

===SystemVerilog===
{{Main|SystemVerilog}}
The advent of [[hardware verification language]]s such as OpenVera, and Verisity's [[e (verification language)|e language]] encouraged the development of [[Superlog HDL|Superlog]] by Co-Design Automation Inc (acquired by [[Synopsys]]). The foundations of Superlog and Vera were donated to [[Accellera]], which later became the IEEE standard P1800-2005: SystemVerilog.

SystemVerilog is a [[superset]] of Verilog-2005, with many new features and capabilities to aid design verification and design modeling. As of 2009, the SystemVerilog and Verilog language standards were merged into SystemVerilog 2009 (IEEE Standard 1800-2009).