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List of Intel processors
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===[[32-bit computing|32-bit]] processors: [[P6 (microarchitecture)|P6]]/[[Pentium M (microarchitecture)|Pentium M]] microarchitecture=== [[File:Intel 80521ex200 256k top.jpg|thumb|Intel Pentium Pro 200 MHz]] ====[[Pentium Pro]]==== * Introduced November 1, 1995 * Multichip Module (2 die) * Precursor to Pentium II and III * Primarily used in server systems * [[Socket 8]] processor package (387 pins; Dual SPGA) * 5.5 million transistors * Family 6 model 1 * [[600 nanometer|0.6 μm process technology]] ** 16 KB L1 cache ** 256 KB integrated [[L2 cache]] ** 60 MHz system bus clock rate ** Variants *** 150 MHz * [[350 nanometer|0.35 μm process technology]], (two die, a 0.35 μm CPU with 0.6 μm L2 cache) ** 5.5 million transistors ** 512 KB or 256 KB integrated L2 cache ** 60 or 66 MHz system bus clock rate ** Variants *** 150 MHz (60 MHz bus clock rate, 256 KB 0.6 μm cache) introduced November 1, 1995 *** 166 MHz (66 MHz bus clock rate, 512 KB 0.35 μm cache) introduced November 1, 1995 *** 180 MHz (60 MHz bus clock rate, 256 KB 0.6 μm cache) introduced November 1, 1995 *** 200 MHz (66 MHz bus clock rate, 256 KB 0.6 μm cache) introduced November 1, 1995 *** 200 MHz (66 MHz bus clock rate, 512 KB 0.35 μm cache) introduced November 1, 1995 *** 200 MHz (66 MHz bus clock rate, 1 MB 0.35 μm cache) introduced August 18, 1997 ====[[Pentium II]]==== * Introduced May 7, 1997 * Pentium Pro with [[MMX (instruction set)|MMX]] and improved [[16-bit computing|16-bit]] performance * 242-pin [[Slot 1]] (SEC) processor package * Voltage identification pins * 7.5 million transistors * 32 KB L1 cache * 512 KB {{frac|1|2}} frequency external L2 cache * The ''Performance Enhanced'' mobile Pentium II (codenamed Dixon) had a full-speed 256 KB L2 cache * '''Klamath''' – [[350 nanometer|0.35 μm process technology]] (233, 266, 300 MHz) ** 66 MHz system bus clock rate ** Family 6 model 3 ** Variants *** 233, 266, 300 MHz introduced May 7, 1997 * '''Deschutes''' – [[250 nanometer|0.25 μm process technology]] (333, 350, 400, 450 MHz) ** Introduced January 26, 1998 ** 66 MHz system bus clock rate (''333 MHz variant''), 100 MHz system bus clock rate for all subsequent models ** Family 6 model 5 ** Variants *** 333 MHz introduced January 26, 1998 *** 350, 400 MHz introduced April 15, 1998 *** 450 MHz introduced August 24, 1998 *** 233, 266 MHz (Mobile) introduced April 2, 1998 *** 333 MHz Pentium II Overdrive processor for Socket 8 Introduced August 10, 1998 *** 300 MHz (Mobile) introduced September 9, 1998 *** 333 MHz (Mobile) introduced January 25, 1999 ====[[Celeron]] (Pentium II-based)==== * '''Covington''' – [[250 nanometer|0.25 μm process technology]] ** Introduced April 15, 1998 ** 242-pin [[Slot 1]] SEPP (Single Edge Processor Package) ** 7.5 million transistors ** 66 MHz system bus clock rate ** Slot 1 ** 32 KB L1 cache ** No L2 cache ** Variants *** 266 MHz introduced April 15, 1998 *** 300 MHz introduced June 9, 1998 * '''Mendocino''' – [[250 nanometer|0.25 μm process technology]] ** Introduced August 24, 1998 ** 242-pin [[Slot 1]] SEPP (Single Edge Processor Package), [[Socket 370]] PPGA package ** 19 million transistors ** 66 MHz system bus clock rate ** Slot 1, Socket 370 ** 32 KB L1 cache ** 128 KB integrated cache ** Family 6 model 6 ** Variants *** 300, 333 MHz introduced August 24, 1998 *** 366, 400 MHz introduced January 4, 1999 *** 433 MHz introduced March 22, 1999 *** 466 MHz *** 500 MHz introduced August 2, 1999 *** 533 MHz introduced January 4, 2000 *** 266 MHz (Mobile) *** 300 MHz (Mobile) *** 333 MHz (Mobile) introduced April 5, 1999 *** 366 MHz (Mobile) *** 400 MHz (Mobile) *** 433 MHz (Mobile) *** 450 MHz (Mobile) introduced February 14, 2000 *** 466 MHz (Mobile) *** 500 MHz (Mobile) introduced February 14, 2000 '''Pentium II Xeon''' ''(chronological entry)'' {{see also|#Pentium II Xeon and Pentium III Xeon}} * Introduced June 29, 1998 ====[[Pentium III]]==== * '''Katmai''' – [[250 nanometer|0.25 μm process technology]] ** Introduced February 26, 1999 ** Improved PII (i.e. P6-based core) now including [[Streaming SIMD Extensions]] (SSE) ** 9.5 million transistors ** 512 KB (512 × 1024 B) {{frac|1|2}} bandwidth L2 External cache ** 242-pin [[Slot 1]] SECC2 (Single Edge Contact cartridge 2) processor package ** System bus clock rate 100 MHz, 133 MHz (B-models) ** Slot 1 ** Family 6 model 7 ** Variants *** 450, 500 MHz introduced February 26, 1999 *** 550 MHz introduced May 17, 1999 *** 600 MHz introduced August 2, 1999 *** 533, 600 MHz introduced (133 MHz bus clock rate) September 27, 1999 * '''Coppermine''' – [[180 nanometer|0.18 μm process technology]] ** Introduced October 25, 1999 ** 28.1 million transistors ** 256 KB (512 × 1024 B) Advanced Transfer L2 cache (integrated) ** 242-pin Slot-1 SECC2 (Single Edge Contact cartridge 2) processor package, 370-pin [[FC-PGA]] (flip-chip pin grid array) package ** System Bus clock rate 100 MHz (E-models), 133 MHz (EB models) ** Slot 1, Socket 370 ** Family 6 model 8 ** Variants *** 500 MHz (100 MHz bus clock rate) *** 533 MHz *** 550 MHz (100 MHz bus clock rate) *** 600 MHz *** 600 MHz (100 MHz bus clock rate) *** 650 MHz (100 MHz bus clock rate) introduced October 25, 1999 *** 667 MHz introduced October 25, 1999 *** 700 MHz (100 MHz bus clock rate) introduced October 25, 1999 *** 733 MHz introduced October 25, 1999 *** 750, 800 MHz (100 MHz bus clock rate) introduced December 20, 1999 *** 850 MHz (100 MHz bus clock rate) introduced March 20, 2000 *** 866 MHz introduced March 20, 2000 *** 933 MHz introduced May 24, 2000 *** 1000 MHz introduced March 8, 2000 (not widely available at time of release) *** 1100 MHz *** 1133 MHz (first version recalled, later re-released) *** 400, 450, 500 MHz (Mobile) introduced October 25, 1999 *** 600, 650 MHz (Mobile) introduced January 18, 2000 *** 700 MHz (Mobile) introduced April 24, 2000 *** 750 MHz (Mobile) introduced June 19, 2000 *** 800, 850 MHz (Mobile) introduced September 25, 2000 *** 900, 1000 MHz (Mobile) introduced March 19, 2001 * '''Tualatin''' – [[130 nanometer|0.13 μm process technology]] ** Introduced July 2001 ** 28.1 million transistors ** 32 KB (32 × 1024 B) L1 cache ** 256 KB or 512 KB Advanced Transfer L2 cache (integrated) ** 370-pin [[FC-PGA2]] (flip-chip pin grid array) package ** 133 MHz system bus clock rate ** Socket 370 ** Family 6 model 11 ** Variants *** 1133 MHz (256 KB L2) *** 1133 MHz (512 KB L2) *** 1200 MHz *** 1266 MHz (512 KB L2) *** 1333 MHz *** 1400 MHz (512 KB L2) ====Pentium II [[Xeon]] and Pentium III Xeon==== * PII Xeon ** Variants *** 400 MHz introduced June 29, 1998 *** 450 MHz (512 KB L2 cache) introduced October 6, 1998 *** 450 MHz (1 MB and 2 MB L2 cache) introduced January 5, 1999 * PIII Xeon ** Introduced October 25, 1999 ** 9.5 million transistors at 0.25 μm or 28 million at 0.18 μm ** L2 cache is 256 KB, 1 MB, or 2 MB Advanced Transfer Cache (Integrated) ** Processor Package Style is Single Edge Contact Cartridge (S.E.C.C.2) or SC330 ** System Bus clock rate 133 MHz (256 KB L2 cache) or 100 MHz (1–2 MB L2 cache) ** System Bus width: 64 bits ** Addressable memory: 64 GB ** Used in two-way servers and workstations (256 KB L2) or 4- and 8-way servers (1–2 MB L2) ** Family 6 model 10 ** Variants *** 500 MHz ([[250 nanometer|0.25 μm process]]) introduced March 17, 1999 *** 550 MHz (0.25 μm process) introduced August 23, 1999 *** 600 MHz ([[180 nanometer|0.18 μm process]], 256 KB L2 cache) introduced October 25, 1999 *** 667 MHz (0.18 μm process, 256 KB L2 cache) introduced October 25, 1999 *** 733 MHz (0.18 μm process, 256 KB L2 cache) introduced October 25, 1999 *** 800 MHz (0.18 μm process, 256 KB L2 cache) introduced January 12, 2000 *** 866 MHz (0.18 μm process, 256 KB L2 cache) introduced April 10, 2000 *** 933 MHz (0.18 μm process, 256 KB L2 cache) *** 1000 MHz (0.18 μm process, 256 KB L2 cache) introduced August 22, 2000 *** 700 MHz (0.18 μm process, 1–2 MB L2 cache) introduced May 22, 2000 ====[[Celeron]] (Pentium III Coppermine-based)==== * Coppermine-128, 0.18 μm process technology ** Introduced March, 2000 ** [[Streaming SIMD Extensions]] (SSE) ** [[Socket 370]], [[FC-PGA]] processor package ** 28.1 million transistors ** 66 MHz system bus clock rate, 100 MHz system bus clock rate from January 3, 2001 ** 32 KB L1 cache ** 128 KB Advanced Transfer L2 cache ** Family 6 model 8 ** Variants *** 533 MHz *** 566 MHz *** 600 MHz *** 633, 667, 700 MHz introduced June 26, 2000 *** 733, 766 MHz introduced November 13, 2000 *** 800 MHz introduced January 3, 2001 *** 850 MHz introduced April 9, 2001 *** 900 MHz introduced July 2, 2001 *** 950, 1000, 1100 MHz introduced August 31, 2001 *** 550 MHz (Mobile) *** 600, 650 MHz (Mobile) introduced June 19, 2000 *** 700 MHz (Mobile) introduced September 25, 2000 *** 750 MHz (Mobile) introduced March 19, 2001 *** 800 MHz (Mobile) *** 850 MHz (Mobile) introduced July 2, 2001 *** 600 MHz (LV Mobile) *** 500 MHz (ULV Mobile) introduced January 30, 2001 *** 600 MHz (ULV Mobile) <big>'''XScale'''</big> ''(chronological entry – non-x86 architecture)'' {{see also|#XScale}} * Introduced August 23, 2000 <big>'''Pentium 4 (not 4EE, 4E, 4F), Itanium, P4-based Xeon, Itanium 2'''</big> ''(chronological entries)'' {{hatnote|See main entries}} * Introduced April 2000 – July 2002 ====Pentium III Tualatin-based==== * Tualatin – [[130 nanometer|0.13 μm process technology]] ** 32 KB L1 cache ** 512 KB Advanced Transfer L2 cache ** 133 MHz system bus clock rate ** Socket 370 ** Variants *** 1.0 GHz *** 1.13 GHz *** 1.26 GHz *** 1.4 GHz ====[[Celeron]] (Pentium III Tualatin-based)==== * Tualatin Celeron – [[130 nanometer|0.13 μm process technology]] ** 32 KB L1 cache ** 256 KB Advanced Transfer L2 cache ** 100 MHz system bus clock rate ** Socket 370 ** Family 6 model 11 ** Variants *** 1.0 GHz *** 1.1 GHz *** 1.2 GHz *** 1.3 GHz *** 1.4 GHz ====[[Pentium M]]==== * '''Banias''' [[130 nanometer|0.13 μm process technology]] ** Introduced March 2003 ** 64 KB L1 cache ** 1 MB L2 cache (integrated) ** Based on Pentium III core, with [[SSE2]] SIMD instructions and deeper pipeline ** 77 million transistors ** [[Micro-FCPGA]], [[Micro-FCBGA]] processor package ** Heart of the Intel mobile ''[[Centrino]]'' system ** 400 MHz NetBurst-style system bus ** Family 6 model 9 ** Variants *** 900 MHz (ultra-low voltage) *** 1.0 GHz (ultra-low voltage) *** 1.1 GHz (low voltage) *** 1.2 GHz (low voltage) *** 1.3 GHz *** 1.4 GHz *** 1.5 GHz *** 1.6 GHz *** 1.7 GHz * '''Dothan''' 0.09 μm ([[90 nanometer|90 nm]]) process technology ** Introduced May 2004 ** 2 MB L2 cache ** 140 million transistors ** Revised data prefetch unit ** 400 MHz NetBurst-style system bus ** 21 W [[thermal design power|TDP]] ** Family 6 model 13 ** Variants *** 1.00 GHz (Pentium M 723) (ultra-low voltage, 5 W TDP) *** 1.10 GHz (Pentium M 733) (ultra-low voltage, 5 W TDP) *** 1.20 GHz (Pentium M 753) (ultra-low voltage, 5 W TDP) *** 1.30 GHz (Pentium M 718) (low voltage, 10 W TDP) *** 1.40 GHz (Pentium M 738) (low voltage, 10 W TDP) *** 1.50 GHz (Pentium M 758) (low voltage, 10 W TDP) *** 1.60 GHz (Pentium M 778) (low voltage, 10 W TDP) *** 1.40 GHz (Pentium M 710) *** 1.50 GHz (Pentium M 715) *** 1.60 GHz (Pentium M 725) *** 1.70 GHz (Pentium M 735) *** 1.80 GHz (Pentium M 745) *** 2.00 GHz (Pentium M 755) *** 2.10 GHz (Pentium M 765) * '''Dothan 533''' 0.09 μm ([[90 nanometer|90 nm]]) process technology ** Introduced Q1 2005 ** Same as '''Dothan''' except with a 533 MHz NetBurst-style system bus and 27 W [[thermal design power|TDP]] ** Variants *** 1.60 GHz (Pentium M 730) *** 1.73 GHz (Pentium M 740) *** 1.86 GHz (Pentium M 750) *** 2.00 GHz (Pentium M 760) *** 2.13 GHz (Pentium M 770) *** 2.26 GHz (Pentium M 780) * '''Stealey''' 0.09 μm ([[90 nanometer|90 nm]]) process technology ** Introduced Q2 2007 ** 512 KB L2, 3 W TDP ** Variants *** 600 MHz (A100) *** 800 MHz (A110) ====[[Celeron|Celeron M]]==== * '''Banias'''-512 [[130 nanometer|0.13 μm]] process technology ** Introduced March 2003 ** 64 KB L1 cache ** 512 KB L2 cache (integrated) ** [[SSE2]] SIMD instructions ** No [[SpeedStep]] technology, is not part of the '[[Centrino]]' package ** Family 6 model 9 ** Variants *** 310, 1.20 GHz *** 320, 1.30 GHz *** 330, 1.40 GHz *** 340, 1.50 GHz * '''Dothan'''-1024 [[90 nanometer|90 nm]] process technology ** 64 KB L1 cache ** 1 MB L2 cache (integrated) ** [[SSE2]] SIMD instructions ** No [[SpeedStep]] technology, is not part of the '[[Centrino]]' package ** Variants *** 350, 1.30 GHz *** 350J, 1.30 GHz, with Execute Disable bit *** 360, 1.40 GHz *** 360J, 1.40 GHz, with Execute Disable bit *** 370, 1.50 GHz, with Execute Disable bit **** Family 6, Model 13, Stepping 8<ref>[http://processorfinder.intel.com/List.aspx?ProcFam=1639 Intel Processor Spec Finder for Celeron M] {{webarchive|url=https://web.archive.org/web/20091103205040/http://processorfinder.intel.com/List.aspx?ProcFam=1639 |date=November 3, 2009}}</ref> *** 380, 1.60 GHz, with Execute Disable bit *** 390, 1.70 GHz, with Execute Disable bit * '''[[Yonah (microprocessor)|Yonah]]'''-1024 [[65 nanometer|65 nm]] process technology ** 64 KB L1 cache ** 1 MB L2 cache (integrated) ** [[SSE3]] SIMD instructions, 533 MHz front-side bus, execute-disable bit ** No [[SpeedStep]] technology, is not part of the '[[Centrino]]' package ** Variants *** 410, 1.46 GHz *** 420, 1.60 GHz, *** 423, 1.06 GHz (ultra-low voltage) *** 430, 1.73 GHz *** 440, 1.86 GHz *** 443, 1.20 GHz (ultra-low voltage) *** 450, 2.00 GHz ====[[Intel Core]]==== * '''[[Yonah (microprocessor)|Yonah]]''' 0.065 μm ([[65 nm]]) process technology ** Introduced January 2006 ** 533/667 MHz [[front-side bus]] ** 2 MB (Shared on Duo) L2 cache ** [[SSE3]] SIMD instructions ** 31W [[Thermal Design Power|TDP]] (T versions) ** Family 6, Model 14 ** Variants: *** Intel Core Duo T2700 2.33 GHz *** Intel Core Duo T2600 2.16 GHz *** Intel Core Duo T2500 2 GHz *** Intel Core Duo T2450 2 GHz *** Intel Core Duo T2400 1.83 GHz *** Intel Core Duo T2300 1.66 GHz *** Intel Core Duo T2050 1.6 GHz *** Intel Core Duo T2300e 1.66 GHz *** Intel Core Duo T2080 1.73 GHz *** Intel Core Duo L2500 1.83 GHz (low voltage, 15 W [[thermal design power|TDP]]) *** Intel Core Duo L2400 1.66 GHz (low voltage, 15 W TDP) *** Intel Core Duo L2300 1.5 GHz (low voltage, 15 W TDP) *** Intel Core Duo U2500 1.2 GHz (ultra-low voltage, 9 W TDP) *** Intel Core Solo T1350 1.86 GHz (533 FSB) *** Intel Core Solo T1300 1.66 GHz *** Intel Core Solo T1200 1.5 GHz<ref>Not listed as an official model by [http://www.intel.com/products/processor/coresolo/ Intel] but used by [[Apple Inc.|Apple]] in their Intel-based [[Mac Mini]], released March 2006 {{webarchive |url=https://web.archive.org/web/20090320220424/http://www.intel.com/products/processor/coresolo/ |date=March 20, 2009}}</ref> ====Dual-Core [[Xeon]] LV==== * '''[[Sossaman (microprocessor)|Sossaman]]''' 0.065 μm ([[65 nm]]) process technology ** Introduced March 2006 ** Based on '''Yonah''' core, with [[SSE3]] SIMD instructions ** 667 MHz [[frontside bus]] ** 2 MB shared L2 cache ** Variants *** 2.0 GHz
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