Editing Xeon (section)

== Sapphire Rapids-based Xeon ==
{{main|Sapphire Rapids (microprocessor)}}Introduced in 2023, the '''4th generation Xeon Scalable''' processors ('''Sapphire Rapids-SP''' and '''Sapphire Rapids-HBM''') and '''Xeon W-2400''' and '''W-3400''' series ('''Sapphire Rapids-WS''') provide large performance enhancements over the prior generation.

=== Features ===

==== CPU ====
{{Further information|Golden Cove (microarchitecture)}}

* Up to 60 [[Golden Cove]] CPU cores per package
* [[AVX-512#FP16|AVX512-FP16]]
* [[Transactional Synchronization Extensions#TSX Suspend Load Address Tracking|TSX Suspend Load Address Tracking (<code>TSXLDTRK</code>)]]
* [[Advanced Matrix Extensions]] (AMX)
* Trust Domain Extensions (TDX), a collection of technologies to help deploy hardware-isolated virtual machines (VMs) called trust domains (TDs)
* In-Field Scan (IFS), a technology that allows for testing the processor for potential hardware faults without taking it completely offline
* Data Streaming Accelerator (DSA), allows for speeding up data copy and transformation between different kinds of storage
* QuickAssist Technology (QAT), allows for improved performance of compression and encryption tasks
* Dynamic Load Balancer (DLB), allows for offloading tasks of load balancing, packet prioritization and queue management
* In-Memory Analytics Accelerator (IAA), allows accelerating in-memory databases and big data analytics

Not all accelerators are available in all processor models. Some accelerators are available under the Intel On Demand program, also known as Software Defined Silicon (SDSi), where a license is required to activate a given accelerator that is physically present in the processor. The license can be obtained as a one-time purchase or as a paid subscription. Activating the license requires support in the operating system. A driver with the necessary support was added in Linux kernel version 6.2.

==== I/O ====

* [[PCI Express#PCI Express 5.0|PCI Express 5.0]]
* [[Direct Media Interface|Direct Media Interface 4.0]]
* 8-channel [[DDR5 SDRAM|DDR5]] memory support up to DDR5-4800, up to 2 DIMMs per channel
* On-package [[High Bandwidth Memory|High Bandwidth Memory 2e]] memory as L4 cache on Xeon Max models
* [[Compute Express Link]] 1.1