Editing Branch (computer science) (section)

=== Delay slot ===
{{Main|Delay slot}}

Another technique is a [[Delay slot|branch delay slot]]. In this approach, at least one instruction following a branch is always executed, with some exceptions such like the legacy [[MIPS architecture]] likely/unlikely branch instruction. Therefore, the computer can use this instruction to do useful work whether or not its pipeline stalls. This approach was historically popular in [[RISC]] computers. In a family of compatible CPUs, it complicates multicycle CPUs (with no pipeline), faster CPUs with longer-than-expected pipelines, and superscalar CPUs (which can execute instructions out of order.)