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Burroughs Large Systems
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==History== {{Expand section|date=June 2008}} <!-- please see the discussion page. I'm attempting to build a table to add to this, but I need help.--> {{notice|In the following discussion, the machine designations, B5000, A Series, and ClearPath/MCP are used interchangeably although this needlessly conflates the features and concepts of the B5000 and B8500 lines with the B6500 line.}} <!-- Should be edited someday to keep clear the distinctions between the 5000/5500/5700, 8300/8500 and 6500 et seq, and A Series. --> The central concept of [[virtual memory]] appeared in the designs of the [[Ferranti Atlas]] and the [[Rice Institute Computer]], and the central concepts of descriptors and tagged architecture appeared in the design of the Rice Institute Computer<ref>{{cite book | title = Capability-Based Computer Systems | author = Henry M. Levy | author-link = Hank Levy (computer scientist) | section = Chapter 2 Early Descriptor Architectures | section-url = https://homes.cs.washington.edu/~levy/capabook/Chapter2.pdf | publisher = Digital Press | url = https://homes.cs.washington.edu/~levy/capabook | mode = cs2}} </ref> in the late 1950s. However, even if those designs had a direct influence on Burroughs, the architectures of the B5000, B6500 and B8500 were very different from those of the Atlas and the Rice machine; they are also very different from each other. The first of the Burroughs large systems was the B5000. Designed in 1961, it was a [[transistor computer|second-generation computer]] using [[discrete transistor]] logic and [[magnetic-core memory]], followed by the B5500 and B5700. The first machines to replace the B5000 architecture were the B6500 and B7500. The successor machines to the B6500 and B7500 followed the hardware development trends to re-implement the architectures in new logic over the next 25 years, with the B6500, B7500, B6700, B7700, B6800, B7800, B5900,<ref group=NB>Despite the model number, the B5900 had a B6500 architecture rather than a B5000 architecture.</ref> B7900 and finally the Burroughs A series. After a merger in which Burroughs acquired [[Sperry Corporation]] and changed its name to [[Unisys]], the company continued to develop new machines based on the '''MCP [[CMOS]]''' [[Application-specific integrated circuit|ASIC]]. These machines were the Libra 100 through the Libra 500, with the Libra 590 being announced in 2005. Later Libras, including the 590, also incorporate Intel Xeon processors and can run the Burroughs large systems architecture in emulation as well as on the MCP CMOS processors. It is unclear if Unisys will continue development of new MCP CMOS ASICs. {| class="wikitable" width="600" align="center" ! style="background: #017A5B;" cellpadding="2" colspan="4" |{{color|white|Burroughs (1961β1986)}} |- text-align="left" | '''B5000'''|| 1961 || initial system, 2nd generation (transistor) computer |- | '''B5500'''|| 1964 || 3x speed improvement<ref name=burroughs3g/><ref name=annltr5500/> |- | '''B6500'''|| 1969 || 3rd generation computer (integrated circuits), up to 4 processors |- | '''B5700'''|| 1971 || new name for B5500{{Disputed inline|Are x700 new names for old products or names for new products|reason=conflicts with sources|date=November 2010}} |- | '''B6700'''|| 1971 || new name/bug fix for B6500{{Disputed inline|Are x700 new names for old products or names for new products|reason=conflicts with sources|date=November 2010}} |- | '''B7700'''|| 1972 || faster processor, cache for stack, up to 8 requestors (I/O or Central processors) in one or two partitions. |- | '''B6800'''|| 1977? || semiconductor memory, [[Non-uniform memory access|NUMA]] architecture |- | '''B7800'''|| 1977? || semiconductor memory, faster, up to 8 requestors (I/O or Central processors) in one or two partitions. |- | '''B6900'''|| 1979? || semiconductor memory, [[Non-uniform memory access|NUMA]] architecture. Max of 4 B6900 CPUs bound to a local memory and a common Global Memory(tm) |- | '''B5900'''|| 1981 || semiconductor memory, [[Non-uniform memory access|NUMA]] architecture. Max of 4 B5900 CPUs bound to a local memory and a common Global Memory II (tm) |- | '''B7900'''|| 1982? || semiconductor memory, faster, code & data caches, [[Non-uniform memory access|NUMA]] architecture, 1-2 HDUs (I/O), 1-2 APs, 1-4 CPUs, Soft implementation of NUMA memory allowed CPUs to float from memory space to memory space. |- | '''A9/A10'''|| 1984 || B6000 class, First pipelined processor in the mid-range, single CPU (dual on A10), First to support eMode Beta (expanded Memory Addressing) |- | '''A12/A15'''|| 1985 || B7000 class, Re-implemented in custom-designed Motorola [[Emitter-coupled logic|ECL]] MCA1, then MCA2 [[gate array]]s, single CPU single HDU (A12) 1β4 CPU, 1β2 HDU (A15) |- |- '''A2/A3/A5'''|| 1985? || B5900 class, A3 (1β2 CPU) followed by low cost A2 (1 CPU) and high performance A5 (1β2 CPU) engineered in Cumbernauld, Scotland |- ! style="background: #017A5B;" cellpadding="2" colspan="4" |{{color|white|Unisys (1986βpresent)}} |- | '''Micro A'''|| 1989 || desktop "mainframe" with single-chip SCAMP<ref>{{cite web |url=http://dunfield.classiccmp.org/other/index.htm#uas |title=Daves Old Computers - Other Machines |at=Unisys A7-311 |access-date=2023-03-30}}</ref><ref>{{Cite web |url=http://dunfield.classiccmp.org/other/h/uascpu.jpg |title=SCAMP picture at dave's Old computers |access-date=2023-03-30}}</ref><ref>{{Citation|last=Reitman|first=Valerie|title=Unisys Ready To Offer A Desktop Mainframe|date=January 18, 1989|newspaper=[[The Philadelphia Inquirer]]|url=http://articles.philly.com/1989-01-18/business/26123789_1_unisys-scamp-mainframe|archive-url=https://web.archive.org/web/20120426182749/http://articles.philly.com/1989-01-18/business/26123789_1_unisys-scamp-mainframe|url-status=dead|archive-date=April 26, 2012|access-date=2011-04-16}}</ref> processor. |- | '''Clearpath HMP NX 4000''' || 1996? || ?<ref name=unisyshist>{{cite web|url=https://www.unisys.com/company-history/|title=Company History|date=9 July 2021|access-date=2021-08-28}}</ref><ref name=unisysTI>{{cite web|url=https://www.tech-insider.org/mainframes/research/1996/04.html|title=Unisys Clears the Path Ahead for A & OS 2200 Series Customers|access-date=2021-08-28}}</ref> |- | '''Clearpath HMP NX 5000''' || 1996? || ?<ref name=unisyshist /><ref name=unisysTI /> |- | '''Clearpath HMP LX 5000''' || 1998 || Implements Burroughs Large systems in emulation only ([[Xeon]] processors)<ref>{{cite press release|url=http://www.highbeam.com/doc/1G1-50063166.html|title=Unisys Accelerates Mainframe Rebirth with New ClearPath Enterprise Servers, Aggressive New Pricing. - Business Wire - HighBeam Research|date=June 8, 1998|archive-url=https://web.archive.org/web/20110516142232/http://www.highbeam.com/doc/1G1-50063166.html|archive-date=May 16, 2011}}</ref> |- | '''Libra 100''' || 2002? || ?? |- | '''Libra 200''' || 200? || ?? |- | '''Libra 300''' || 200? || ?? |- | '''Libra 400''' || 200? || ?? |- | '''Libra 500''' || 2005? || e.g. Libra 595<ref>{{cite web|url=https://www.app5.unisys.com/offerings/ClearPathConnection/2q2008_5.htm|title=Libra 595|publisher=Unisys}}</ref> |- | '''Libra 600''' || 2006? || ?? |- | '''Libra 700''' || 2010 || e.g. Libra 750<ref>{{cite web|url=https://www.unisys.com/news/news%20release/unisys-expands-support-for-modernized-applications-and-mobile-devices-on-clearpath-mainframes|title=Libra 750|date=24 June 2021|publisher=Unisys|access-date=16 May 2018|archive-date=11 March 2020|archive-url=https://web.archive.org/web/20200311074623/https://www.unisys.com/news/news%20release/unisys-expands-support-for-modernized-applications-and-mobile-devices-on-clearpath-mainframes|url-status=dead}}</ref> |}
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