Editing Classic RISC pipeline (section)

===Structural hazards===

'''Structural hazards occur when two instructions might attempt to use the same resources at the same time.'''  Classic RISC pipelines avoided these hazards by replicating hardware.  In particular, branch instructions could have used the ALU to compute the target address of the branch.  If the ALU were used in the decode stage for that purpose, an ALU instruction followed by a branch would have seen both instructions attempt to use the ALU simultaneously.  It is simple to resolve this conflict by designing a specialized branch target adder into the decode stage.