Editing Clock signal (section)

== Distribution ==
The most effective way to get the clock signal to every part of a chip that needs it, with the lowest [[clock skew|skew]], is a metal grid. In a large microprocessor, the power used to drive the clock signal can be over 30% of the total power used by the entire chip. The whole structure with the gates at the ends and all amplifiers in between have to be loaded and unloaded every cycle.<ref>{{citation |url=http://www.anandtech.com/showdoc.aspx?i=3276&p=14 |title=Intel's Atom Architecture: The Journey Begins |author=Anand Lal Shimpi |year=2008}}</ref><ref>{{citation |url=http://alasir.com/articles/alpha_history/alpha_21264.html |title=Alpha: The history in facts and comments |author=Paul V. Bolotoff |year=2007 |quote=power consumed by the clock subsystem of EV6 was about 32% of the total core power. To compare, it was about 25% for EV56, about 37% for EV5 and about 40% for EV4. |access-date=2012-01-03 |archive-url=https://web.archive.org/web/20120218005309/http://alasir.com/articles/alpha_history/alpha_21264.html |archive-date=2012-02-18 |url-status=dead }}</ref> To save energy, [[clock gating]] temporarily shuts off part of the tree.

The '''clock distribution network''' (or '''clock tree''', when this network forms a tree such as an [[H-tree]]) distributes the clock signal(s) from a common point to all the elements that need it. Since this function is vital to the operation of a synchronous system, much attention has been given to the characteristics of these clock signals and the [[electrical network]]s used in their distribution. Clock signals are often regarded as simple control signals; however, these signals have some very special characteristics and attributes.

Clock signals are typically loaded with the greatest [[fanout]] and operate at the highest speeds of any signal within the synchronous system. Since the data signals are provided with a temporal reference by the clock signals, the clock [[waveform]]s must be particularly clean and sharp. Furthermore, these clock signals are particularly affected by technology scaling (see [[Moore's law]]), in that long [[global interconnect]] lines become significantly more resistive as line dimensions are decreased. This increased line resistance is one of the primary reasons for the increasing significance of clock distribution on synchronous performance. Finally, the control of any differences and uncertainty in the arrival times of the clock signals can severely limit the maximum performance of the entire system and create [[Race hazard|race conditions]] in which an incorrect data signal may latch within a register.

Most synchronous [[Digital data|digital]] systems consist of cascaded banks of sequential [[Flip-flop (electronics)|registers]] with [[combinational logic]] between each set of registers. The functional requirements of the digital system are satisfied by the logic stages. Each logic stage introduces delay that affects timing performance, and the timing performance of the digital design can be evaluated relative to the timing requirements by a timing analysis. Often special considerations must be given in order to meet the timing requirements. For example, the global performance and local timing requirements may be satisfied by the careful insertion of [[Pipeline (computing)|pipeline registers]] into equally spaced time windows to satisfy critical worst-case [[timing constraints]]. A proper design of the clock distribution network helps ensure that critical timing requirements are satisfied and that no race conditions exist (see also [[clock skew]]).

The delay components that make up a general synchronous system are composed of three individual subsystems: the memory storage elements, the logic elements, and the clocking circuitry and distribution network.

Novel structures are currently under development to ameliorate these issues and provide effective solutions. Important areas of research include resonant clocking techniques ("resonant clock mesh"),<ref>
{{Cite journal
| doi=10.1109/JSSC.2004.838005
| bibcode=2005IJSSC..40..102C
| title=Uniform-phase uniform-amplitude resonant-load global clock distributions
| last1=Chan| first1=S. C.
| last2=Shepard| first2=K. L.
| last3=Restle| first3=P. J.
| journal=IEEE Journal of Solid-State Circuits
| volume=40
| issue=1| pages=102
| year=2005
| s2cid=16239014}}
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David Shan et. al.
[https://ieeexplore.ieee.org/abstract/document/7231308 "Resonant clock mega-mesh for the IBM z13"].
2015.
</ref><ref>
Wulong Liu; Guoqing Chen; Yu Wang; Huazhong Yang.
[https://ieeexplore.ieee.org/document/7059052 "Modeling and optimization of low power resonant clock mesh"].
2015.</ref><ref>
[https://www.techdesignforums.com/practice/guides/clock-tree-synthesis-distribution-strategies/ "Clock tree synthesis"].
</ref>
on-chip optical interconnect, and [[globally asynchronous locally synchronous|local synchronization]] methodologies.