Editing Compatible Time-Sharing System (section)

===Kernel===
CTSS used a modified IBM 7090 mainframe computer<ref>{{cite web |url=https://people.csail.mit.edu/saltzer/Multics/CTSS-Documents/RPQs/RPQs.html |title=Documents describing special hardware for CTSS |access-date=2024-04-21 |archive-date=2024-06-25 |archive-url=https://web.archive.org/web/20240625150843/https://people.csail.mit.edu/saltzer/Multics/CTSS-Documents/RPQs/RPQs.html |url-status=live }}</ref> that had two 32,768 (32K) 36-bit-[[Word (computer architecture)|word]] banks of [[core memory]] instead of the default configuration which provides only one.<ref name="osc">{{cite book |title=Operating System Concepts |chapter=13: Historical Perspective |page=514 |first1=Abraham |last1=Silberschatz |first2=James L. |last2=Peterson |date=June 1988 |publisher=Addison-Wesley |isbn=0-201-18760-4}}</ref><ref>{{cite book |url=https://people.csail.mit.edu/saltzer/Multics/CTSS-Documents/RPQs/L22-6636-1.pdf |title=IBM 7090 and 7094 Data Processing Systems Additional Core Storage - RPO E02120 (7090) Dr RPO E15724 (7094) |series=Special Systems Features Bulletin |publisher=IBM |id=L22-6636-1}}</ref> One bank was reserved for the time-sharing supervisory program, the other for user programs. CTSS had a protected-mode kernel; the supervisor's functions in the A-core (memory bank A) could be called only by software interrupts, as in modern operating systems. Causing memory-protection interrupts were used for software interrupts.<ref name="ctsspg63" /> [[Central processing unit|Processor]] allocation [[Scheduling (computing)|scheduling]] with a quantum time unit 200 ms, was controlled by a [[multilevel feedback queue]].<ref name="osc"/> It also had some special memory-management hardware,<ref name="multiprogramming-package">{{cite book |url=https://people.csail.mit.edu/saltzer/Multics/CTSS-Documents/RPQs/L22-6641-3.pdf |title=IBM 7090-7094 Multiprogramming Package RPO E07291 (7090) or RPO 880287 (7094) |series=Special Systems Features Bulletin |publisher=IBM |id=L22-6641-3}}</ref> a clock interrupt,<ref>{{cite book |url=https://people.csail.mit.edu/saltzer/Multics/CTSS-Documents/RPQs/L22-6554-1.pdf |title=Core Storage Clock and Interval Timer - RPO FB9349 |series=Special Systems Features Bulletin |publisher=IBM |id=L22-6554-1 |access-date=2024-04-21 |archive-date=2023-04-08 |archive-url=https://web.archive.org/web/20230408045855/https://people.csail.mit.edu/saltzer/Multics/CTSS-Documents/RPQs/L22-6554-1.pdf |url-status=live }}</ref> and the ability to trap certain instructions.<ref name="multiprogramming-package" />