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Cyrix 6x86
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=== Model table === {| class="wikitable mw-collapsible mw-collapsed" !Images !Model !Core name !Process size<br />([[Micrometre|ΞΌm]]) !Die area<br />([[Square millimeter|mm<sup>2</sup>]]) !Number of transistors<br />(millions) !Socket(s) !Package !Core Voltage !TDP (W) !Clock speed !Bus Speed !L1 Cache !Price (USD) !Launch |- | rowspan="6" |<gallery mode="nolines" widths="80" heights="80" perrow="1" style="margin-left: auto; margin-right: auto;"> File:KL Cyrix 6x86.jpg File:Cyrix 6x86-P166.jpg </gallery> |PR90+ |M1 |0,65 |394 |3.0 |[[Socket 7]] |[[Ceramic Pin Grid Array|CPGA]] |3.3 |15.5 |80 MHz |40 MHz |16 KB |$84 |Nov 1995 |- |PR120+ |M1 |0,65 |394 |3.0 |[[Socket 7]] |[[Ceramic Pin Grid Array|CPGA]] |3.3 |? |100 MHz |50 MHz |16 KB |$450 |Oct 1995 |- |PR133+ |M1R |0,65 |225 |3.0 |[[Socket 7]] |[[Ceramic Pin Grid Array|CPGA]] |3.3 |19.1 |110 MHz |55 MHz |16 KB |$326 |2-5-1996 |- |PR150+ |M1R |0,65 |225 |3.0 |[[Socket 7]] |[[Ceramic Pin Grid Array|CPGA]] |3.3/3.52 |20.1 |120 MHz |60 MHz |16 KB |$451 |2-5-1996 |- |PR166+ |M1R |0,65 |225 |3.0 |[[Socket 7]] |[[Ceramic Pin Grid Array|CPGA]] |3.3/3.52 |21.8 |133 MHz |66 MHz |16 KB |$621 |2-5-1996 |- |PR200+ |M1R |0,44 |? |3.0 |[[Socket 7]] |[[Ceramic Pin Grid Array|CPGA]] |3.52 |17.13 |150 MHz |75 MHz |16 KB |$499 |6-6-1996 |- | rowspan="5" |<gallery mode="nolines" widths="80" heights="80" perrow="1" style="margin-left: auto; margin-right: auto;"> File:Cyrix6x86L-PR166.jpg File:KL Cyrix 6x86L.jpg </gallery> |L-PR120+ |M1L |0,35 |169 |3.0 |[[Socket 7]] |[[Ceramic Pin Grid Array|CPGA]] |2.8/3.3 |? |100 MHz |50 MHz |16 KB |? |Jan-1997 |- |L-PR133+ |M1L |0,35 |169 |3.0 |[[Socket 7]] |[[Ceramic Pin Grid Array|CPGA]] |2.8/3.3 |? |110 MHz |55 MHz |16 KB |? |Feb-1997 |- |L-PR150+ |M1L |0,35 |169 |3.0 |[[Socket 7]] |[[Ceramic Pin Grid Array|CPGA]] |2.8/3.3 |? |120 MHz |60 MHz |16 KB |? |Mar-1997 |- |L-PR166+ |M1L |0,35 |169 |3.0 |[[Socket 7]] |[[Ceramic Pin Grid Array|CPGA]] |2.8/3.3 |15.98 |133 MHz |66 MHz |16 KB |? |Apr-1997 |- |L-PR200+ |M1L |0,35 |169 |3.0 |[[Socket 7]] |[[Ceramic Pin Grid Array|CPGA]] |2.8/3.3 |17.13 |150 MHz |75 MHz |16 KB |? |Apr-1997 |- | rowspan="4" |<gallery mode="nolines" widths="80" heights="80" perrow="1" style="margin-left: auto; margin-right: auto;"> File:KL Cyrix 6x86MX.jpg File:Ic-photo-Cyrix--6x86MX-PR233--(6x86MX-CPU).png </gallery> |PR166-MMX |MII |0,35 |197 |6.0 |[[Socket 7]] |[[Ceramic Pin Grid Array|CPGA]] |2.9/3.3 |? ? |133 MHz 150 MHz |66 MHz 60 MHz |64 KB |$190 ? |5-30-97 Q2 1998 |- |PR200-MMX |MII |0,35 ([[IBM]]) 0,30 ([[National Semiconductor|NS]]) |197 156 |6.0 |[[Socket 7]] |[[Ceramic Pin Grid Array|CPGA]] |2.9/3.3 |? ? |150 MHz 166 MHz |75 MHz 66 MHz |64 KB |$240 ? |5-30-97 Q2 1998 |- |PR233-MMX |MII |0,35 ([[IBM]]) 0,30 ([[National Semiconductor|NS]]) |197 156 |6.0 |[[Socket 7]] |[[Ceramic Pin Grid Array|CPGA]] |2.9/3.3 |? ? |188 MHz 200 MHz |75 MHz 66 MHz |64 KB |$320 ? |5-30-97 Q2 1998 |- |PR266-MMX |MII |0,35 ([[IBM]]) 0,30 ([[National Semiconductor|NS]]) |197 156 |6.0 |[[Socket 7]] |[[Ceramic Pin Grid Array|CPGA]] |2.9/3.3 |? |208 MHz |83 MHz |64 KB |$180 ? |3-19-98 Q2 1998 |- | rowspan="6" |<gallery mode="nolines" widths="80" heights="80" perrow="1" style="margin-left: auto; margin-right: auto;"> File:Cyrix-m2-233gp 75x2.5.jpg File:KL Cyrix MII-333.jpg File:Cyrix M II-433GP - 300MHz CPU 1998 front.jpg </gallery> |MII-300-MMX (*m) |MII |0,30 0,25 |156 88 |6.0 |[[Super Socket 7|Super 7]] |[[Ceramic Pin Grid Array|CPGA]] |2.9/3.3 2.2 (*m) |? ? |233 MHz 225 MHz |66 MHz 75 MHz |64 KB |$180 ? |4-14-98 Q1 1999 |- |MII-333-MMX (*m) |MII |0,30 0,25 |156 88 |6.0 |[[Super Socket 7|Super 7]] |[[Ceramic Pin Grid Array|CPGA]] |2.9/3.3 2.2 (*m) |? ? |250 MHz |100 MHz 83 MHz |64 KB |$180 ? |6-15-98 Mar-1999 |- |MII-350-MMX |MII |0,25 |88 |6.0 |[[Super Socket 7|Super 7]] |[[Ceramic Pin Grid Array|CPGA]] |2.9/3.3 |? |270 MHz 250 MHz |90 MHz 83 MHz |64 KB |? ? |? ? |- |MII-366-MMX |MII |0,25 |88 |6.0 |[[Super Socket 7|Super 7]] |[[Ceramic Pin Grid Array|CPGA]] |2.9/3.3 |? |250 MHz |100 MHz |64 KB |? |Mar-1999 |- |MII-400-MMX (*m) |MII |0,18 |65 |6.0 |[[Super Socket 7|Super 7]] |[[Ceramic Pin Grid Array|CPGA]] |2.2/3.3 |? |285 MHz |95 MHz |64 KB |? |Jun-1999 |- |MII-433-MMX (*m) |MII |0,18 |65 |6.0 |[[Super Socket 7|Super 7]] |[[Ceramic Pin Grid Array|CPGA]] |2.2/3.3 |? |300 MHz |100 MHz |64 KB |? |Jun-1999 |- | rowspan="7" |<gallery mode="nolines" widths="80" heights="80" perrow="1" style="margin-left: auto; margin-right: auto;"> File:Cyrix 6x86 P150+ CPU.jpg </gallery> ! colspan="14" |SGS-Thomson 6x86 Models |- |ST6x86P90+HS |M1 |0,65 |394 |3.0 |[[Socket 7]] |[[Ceramic Pin Grid Array|CPGA]] |3.52 |17.39 |80 MHz |40 MHz |16 KB |? |? |- |ST6x86P120+HS |M1 |0,65 |394 |3.0 |[[Socket 7]] |[[Ceramic Pin Grid Array|CPGA]] |3.52 |19.98 |100 MHz |50 MHz |16 KB |? |2-5-1996 |- |ST6x86P133+HS |M1 |0,65 |394 |3.0 |[[Socket 7]] |[[Ceramic Pin Grid Array|CPGA]] |3.52 |21.46 |110 MHz |55 MHz |16 KB |? |2-5-1996 |- |ST6x86P150+HS |M1 |0,65 |225 |3.0 |[[Socket 7]] |[[Ceramic Pin Grid Array|CPGA]] |3.52 |? |120 MHz |60 MHz |16 KB |? |2-5-1996 |- |ST6x86P166+HS |M1 |0,65 |225 |3.0 |[[Socket 7]] |[[Ceramic Pin Grid Array|CPGA]] |3.52 |? |133 MHz |66 MHz |16 KB |? |2-5-1996 |- |ST6x86P200+HS |M1 |0,44 |? |3.0 |[[Socket 7]] |[[Ceramic Pin Grid Array|CPGA]] |3.52 |? |150 MHz |75 MHz |16 KB |? |? |- | rowspan="7" |<gallery mode="nolines" widths="80" heights="80" perrow="1" style="margin-left: auto; margin-right: auto;"> File:IBM 6x86 P150+ CPU.jpg File:KL IBM 6x86 P166+ Cyrix.jpg </gallery> ! colspan="14" |IBM 6x86 Models |- |<sub>2V2100 GB</sub> |M1 |0,65 |394 |3.0 |[[Socket 7]] |[[Ceramic Pin Grid Array|CPGA]] |3.3 |? |80 MHz |40 MHz |16 KB |? |? |- |<sub>2V2P120GC</sub> |M1 |0,65 |394 |3.0 |[[Socket 7]] |[[Ceramic Pin Grid Array|CPGA]] |3.3 |? |100 MHz |50 MHz |16 KB |? |? |- |<sub>2V2120 GB</sub> |M1R |0,65 |394 |3.0 |[[Socket 7]] |[[Ceramic Pin Grid Array|CPGA]] |3.33 |? |100 MHz |50 MHz |16 KB |? |? |- |<sub>2V2P150GE</sub> |M1R |0,65 |225 |3.0 |[[Socket 7]] |[[Ceramic Pin Grid Array|CPGA]] |3.3/3.52 |? |120 MHz |60 MHz |16 KB |? |2-5-1996 |- |<sub>2V2P166GE</sub> |M1R |0,65 |225 |3.0 |[[Socket 7]] |[[Ceramic Pin Grid Array|CPGA]] |3.3/3.52 |21.8 |133 MHz |66 MHz |16 KB |? |2-5-1996 |- |<sub>2V7P200GE</sub> |M1R |0,44 |? |3.0 |[[Socket 7]] |[[Ceramic Pin Grid Array|CPGA]] |3.52 |14 |150 MHz |75 MHz |16 KB |? |2-5-1996 |- | rowspan="4" |<gallery mode="nolines" widths="80" heights="80" perrow="1" style="margin-left: auto; margin-right: auto;"> File:KL IBM 6x86L Cyrix.jpg </gallery> |<sub>2VAP120 GB</sub> |M1L |0,35 |169 |3.0 |[[Socket 7]] |[[Ceramic Pin Grid Array|CPGA]] |2.8 |? |100 MHz |50 MHz |16 KB |? |? |- |<sub>2VAP150 GB</sub> |M1L |0,35 |169 |3.0 |[[Socket 7]] |[[Ceramic Pin Grid Array|CPGA]] |2.8 |? |120 MHz |60 MHz |16 KB |? |? |- |<sub>2VAP166 GB</sub> |M1L |0,35 |169 |3.0 |[[Socket 7]] |[[Ceramic Pin Grid Array|CPGA]] |2.8 |? |133 MHz |66 MHz |16 KB |? |? |- |<sub>2VAP200 GB</sub> |M1L |0,35 |169 |3.0 |[[Socket 7]] |[[Ceramic Pin Grid Array|CPGA]] |2.8 |? |150 MHz |75 MHz |16 KB |? |? |- | rowspan="12" |<gallery mode="nolines" widths="80" heights="80" perrow="1" style="margin-left: auto; margin-right: auto;"> File:KL IBM 6x86MX.jpg File:Cyrix IBM CPU 6x86MX PR200 top.jpg File:IBM PR300.jpg </gallery> |<sub>AVAPR166 GB</sub> |MII |0,35 |197 |6.0 |[[Socket 7]] |[[Ceramic Pin Grid Array|CPGA]] |2.9/3.3 |? |133 MHz |66 MHz |64 KB |$202 |5-30-97 |- |? |MII |0,35 |197 |6.0 |[[Socket 7]] |[[Ceramic Pin Grid Array|CPGA]] |2.9/3.3 |? |150 MHz |60 MHz |64 KB |? |5-30-97 |- |<sub>BVAPR200 GB</sub> |MII |0,35 |? |6.0 |[[Socket 7]] |[[Ceramic Pin Grid Array|CPGA]] |2.9/3.3 |? |150 MHz |75 MHz |64 KB |$369 |5-30-97 |- |<sub>AVAPR200GA</sub> |MII |0,30 |? |6.0 |[[Socket 7]] |[[Ceramic Pin Grid Array|CPGA]] |2.9/3.3 |? |166 MHz |66 MHz |64 KB |? |Q2 1998 |- |<sub>BVAPR233GC</sub> |MII |0,35 |? |6.0 |[[Socket 7]] |[[Ceramic Pin Grid Array|CPGA]] |2.9/3.3 |? |166 MHz |83 MHz |64 KB |$477 |5-30-97 |- |<sub>AVAPR233 GB</sub> |MII |0,30 |? |6.0 |[[Socket 7]] |[[Ceramic Pin Grid Array|CPGA]] |2.9/3.3 |? |188 MHz |75 MHz |64 KB |? |Q2 1998 |- |<sub>BVAPR233GD</sub> |MII |0,30 |? |6.0 |[[Socket 7]] |[[Ceramic Pin Grid Array|CPGA]] |2.9/3.3 |? |200 MHz |66 MHz |64 KB |? |Q2 1998 |- |<sub>BVAPR266GE</sub> |MII |0,35 0,30 |? |6.0 |[[Socket 7]] |[[Ceramic Pin Grid Array|CPGA]] |2.9/3.3 |? |208 MHz |83 MHz |64 KB |? |3-19-98 Q2 1998 |- |<sub>CVAPR300GF (*m)</sub> |MII |0,25 |119 |6.0 |[[Super Socket 7|Super 7]] |[[Ceramic Pin Grid Array|CPGA]] |2.9/3.3 |? |225 MHz |75 MHz |64 KB |$217 |3-19-98 |- |<sub>DVAPR300GF (*m)</sub> |MII |0,25 |119 |6.0 |[[Super Socket 7|Super 7]] |[[Ceramic Pin Grid Array|CPGA]] |2.9/3.3 |? |233 MHz |66 MHz |64 KB |? |? |- |<sub>CVAPR333GF (*m)</sub> |MII |0,25 |119 |6.0 |[[Super Socket 7|Super 7]] |[[Ceramic Pin Grid Array|CPGA]] |2.9/3.3 2.2 (*m) |? |250 MHz |83 MHz |64 KB |$299 |3-19-98 |- |? |MII |0,25 |119 |6.0 |[[Super Socket 7|Super 7]] |[[Ceramic Pin Grid Array|CPGA]] |2.9/3.3 |? |263 MHz |75 MHz |64 KB |? |? |- | colspan="15" |? - Missing information <nowiki>*</nowiki>m -Available in mobile version for laptops Information From: * https://www.pchardwarelinks.com/586.htm * https://www.cpu-world.com/CPUs/6x86/ * https://www.x86-guide.net/ * http://www.cpu-galerie.de/ |}
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