Editing Deflate (section)

=== Hardware encoders ===
* AHA361-PCIX/AHA362-PCIX from [https://www.aha.com/ Comtech AHA] {{Webarchive|url=https://web.archive.org/web/20061208005415/http://www.aha.com/ |date=2006-12-08}}. Comtech produced a [[PCI-X]] card (PCI-ID: <code>193f:0001</code>) able to compress streams using Deflate at a rate of up to 3.0&nbsp;Gbit/s (375&nbsp;MB/s) for incoming uncompressed data. Accompanying the [[Linux kernel]] [[device driver]] for the AHA361-PCIX is an "<code>ahagzip</code>" utility and customized "<code>mod_deflate_aha</code>" able to use the hardware compression from [[Apache HTTP Server|Apache]]. The hardware is based on a [[Xilinx]] [[Virtex (FPGA)|Virtex]] [[field-programmable gate array]] (FPGA) and four custom AHA3601 [[application-specific integrated circuit]]s (ASICs). The AHA361/AHA362 boards are limited to only handling static Huffman blocks and require software to be modified to add support. The cards could not support the full Deflate specification, meaning they could only reliably decode their own output (a stream that did not contain any dynamic Huffman type 2 blocks).
* [https://web.archive.org/web/20080204071759/https://www.indranetworks.com/SC300.html StorCompress 300]/[https://www.indranetworks.com/SCMX3.html MX3] from [https://www.indranetworks.com/ Indra Networks]. This is a range of [[Peripheral Component Interconnect]] (PCI, PCI-ID: <code>17b4:0011</code>) or PCI-X cards featuring between one and six compression engines with claimed processing speeds of up to 3.6&nbsp;Gbit/s (450&nbsp;MB/s). A version of the cards are available with the separate brand ''WebEnhance'' specifically designed for web-serving use rather than [[storage area network]] (SAN) or backup use; a [[PCI Express]] (PCIe) revision, the [http://www.indranetworks.com/SCMX4E.html MX4E] is also produced.
* [https://web.archive.org/web/20080912222617/http://www.aha.com/show_prod.php?id=36 AHA363-PCIe]/[https://web.archive.org/web/20090212202014/http://www.aha.com/show_prod.php?id=37 AHA364-PCIe]/[https://web.archive.org/web/20090820184941/http://www.aha.com/show_prod.php?id=38 AHA367-PCIe]. In 2008, Comtech started producing two PCIe cards (<code>PCI-ID: 193f:0363</code>/<code>193f:0364</code>) with a new hardware AHA3610 encoder chip. The new chip was designed to be capable of a sustained 2.5&nbsp;Gbit/s. Using two of these chips, the AHA363-PCIe board can process Deflate at a rate of up to 5.0&nbsp;Gbit/s (625&nbsp;MB/s) using the two channels (two compression and two decompression). The AHA364-PCIe variant is an encode-only version of the card designed for out-going [[load balancer]]s and instead has multiple register sets to allow 32 independent ''virtual'' compression channels feeding two physical compression engines. Linux, [[Microsoft Windows]], and [[OpenSolaris]] kernel device drivers are available for both of the new cards, along with a modified zlib system library so that dynamically linked applications can automatically use the hardware support without internal modification. The AHA367-PCIe board (<code>PCI-ID: 193f:0367</code>) is similar to the AHA363-PCIe but uses four AHA3610 chips for a sustained compression rate of 10&nbsp;Gbit/s (1250&nbsp;MB/s). Unlike the AHA362-PCIX, the decompression engines on the AHA363-PCIe and AHA367-PCIe boards are fully deflate compliant.
* [https://web.archive.org/web/20101203144755/http://www.cavium.com/processor_security_nitrox-III.html Nitrox] and [https://github.com/zerix/Cavium-SDK-2.0/tree/master/examples/zip Octeon]{{Dead link|date=November 2019 |bot=InternetArchiveBot |fix-attempted=yes}} processors from [http://cavium.com Cavium, Inc.] contain high-speed hardware deflate and inflate engines compatible with both ZLIB and GZIP with some devices able to handle multiple simultaneous data streams.
* [https://github.com/tomtor/HDL-deflate HDL-Deflate] GPL FPGA implementation.
*[https://www.cast-inc.com/compression/gzip-lossless-data-compression/zipaccel-c/ ZipAccel-C] from [https://www.cast-inc.com/ CAST Inc]. This is a Silicon IP core supporting Deflate, [[Zlib]] and [[Gzip]] compression. ZipAccel-C can be implemented in [[Application-specific integrated circuit|ASIC]] or [[field-programmable gate array]] (FPGAs), supports both Dynamic and Static Huffman tables, and can provide throughputs in excess of 100&nbsp;Gbit/s. The company offers compression/decompression accelerator board reference designs for Intel FPGA ([https://www.cast-inc.com/compression/gzip-lossless-data-compression/gzip-rd-int/ ZipAccel-RD-INT]) and Xilinx FPGAs ([https://www.cast-inc.com/compression/gzip-lossless-data-compression/gzip-rd-xil/ ZipAccel-RD-XIL]).
* [[Intel Xeon chipsets|Intel Communications Chipset 89xx Series]] (Cave Creek) for the [[Intel]] [[Xeon]] E5-2600 and E5-2400 Processor Series (Sandy Bridge-EP/EN) supports hardware compression and decompression using QuickAssist Technology. Depending on the chipset, compression and decompression rates of 5&nbsp;Gbit/s, 10&nbsp;Gbit/s, or 20&nbsp;Gbit/s are available.<ref name="quickassist">{{cite web
|url=https://www-ssl.intel.com/content/www/us/en/intelligent-systems/crystal-forest-server/embedded-intel-xeon-e5-2600-and-e5-2400-series-with-intel-communications-chipset-89xx.html
|title=Intel Xeon Processor E5-2600 and E5-2400 Series with Intel Communications Chipset 89xx Series
|access-date=2016-05-18
}}</ref>
* [[IBM z15 (microprocessor)|IBM z15]] CPUs incorporate an improved version of the Nest Accelerator Unit (NXU) hardware acceleration from the zEDC Express [[input/output]] (I/O) expansion cards used in z14 systems for hardware Deflate compression and decompression as specified by RFC1951.<ref name="z15_announce">{{cite web
|url=https://www.ibm.com/common/ssi/cgi-bin/ssialias?subtype=ca&infotype=an&supplier=877&letternum=ENUSZG19-0041
|title=Introducing the IBM z15 - The enterprise platform for mission-critical hybrid multicloud
|website=[[IBM]]
|date=12 September 2019
|access-date=2021-11-01
}}</ref><ref name="z15_techmanual">{{cite book
|url=https://books.google.com/books?id=0vr3DwAAQBAJ&dq=%22Nest+accelerator%22&pg=PA97
|title=IBM z15 (8562) Technical Guide, Page 97
|isbn=9780738458991
|access-date=2021-11-01
|last1=Lascu
|first1=Octavian
|date=28 April 2021
|publisher=IBM Redbooks
}}</ref>
* Starting with the [[POWER9]] architecture, IBM added hardware support for compressing and decompressing Deflate (as specified by RFC 1951) to the formerly crypto-centric Nest accelerator (NX) core introduced with [[POWER7]]+. This support is available to programs running with [[IBM AIX|AIX]] 7.2 Technology Level 4 Expansion Pack or AIX 7.2 Technology Level 5 Service Pack 2 through the zlibNX library.<ref name="zlibnx">{{cite web
|url=https://www.ibm.com/docs/en/aix/7.2?topic=management-data-compression-by-using-zlibnx-library
|title=Data compression by using the zlibNX library - IBM Documentation
|website=[[IBM]]
|access-date=2021-11-01
}}</ref><ref name="power7_accel">{{cite web
|url=https://community.ibm.com/community/user/power/blogs/xinya-wang1/2021/02/18/exploitation-of-nest-accelerators-and-in-core-acce
|title=Exploitation of In-Core Acceleration of POWER Processors for AIX
|access-date=2021-11-01
}}</ref>