Editing Digital signal processor (section)

====Memory architecture====

DSPs are usually optimized for streaming data and use special memory architectures that are able to fetch multiple data or instructions at the same time, such as the [[Harvard architecture]] or Modified [[von Neumann architecture]], which use separate program and data memories (sometimes even concurrent access on multiple data buses).

DSPs can sometimes rely on supporting code to know about cache hierarchies and the associated delays. This is a tradeoff that allows for better performance{{clarify|date=November 2015}}. In addition, extensive use of [[Direct memory access|DMA]] is employed.

=====Addressing and virtual memory=====

DSPs frequently use multi-tasking operating systems, but have no support for [[virtual memory]] or memory protection. Operating systems that use virtual memory require more time for [[context switching]] among [[process (computing)|processes]], which increases latency.

*Hardware modulo addressing
**Allows [[circular buffer]]s to be implemented without having to test for wrapping
*Bit-reversed addressing, a special [[addressing mode]]
**useful for calculating FFTs
*Exclusion of a [[memory management unit]]
*[[Address generation unit]]