Editing Electronic design automation (section)

=== Analysis and verification ===
* [[Functional verification]]: ensures [[Circuit (computer science)|logic design]] matches specifications and executes tasks correctly. Includes dynamic functional verification via simulation, emulation, and prototypes.<ref>{{Cite web |date=March 17, 2017 |title=Functional Verification |url=https://semiengineering.com/knowledge_centers/eda-design/verification/functional-verification/ |access-date=April 10, 2023 |website=Semiconductor Engineering}}</ref>
* RTL Linting for adherence to coding rules such as syntax, semantics, and style.<ref>BTV [https://besttechviews.com/rtl-linting-tools-reviews-metrics/ RTL Linting.] Retrieved January 2, 2023</ref>
*[[Clock domain crossing|Clock domain crossing verification]] (CDC check): similar to [[Lint programming tool|linting]], but these checks/tools specialize in detecting and reporting potential issues like [[data loss]], [[Metastability in electronics|meta-stability]] due to use of multiple [[clock domain]]s in the design.
* [[Formal verification]], also [[model checking]]: attempts to prove, by mathematical methods, that the system has certain desired properties, and that some undesired effects (such as [[deadlock (computer science)|deadlock]]) cannot occur.
* [[Formal equivalence checking|Equivalence checking]]: algorithmic comparison between a chip's RTL-description and synthesized gate-[[netlist]], to ensure functional equivalence at the ''logical'' level.
* [[Static timing analysis]]: analysis of the timing of a circuit in an input-independent manner, hence finding a worst case over all possible inputs.
* [[Layout extraction]]: starting with a proposed layout, compute the (approximate) electrical characteristics of every wire and device.  Often used in conjunction with static timing analysis above to estimate the performance of the completed chip.
* [[Electromagnetic field solver]]s, or just [[Electromagnetic field solver|field solvers]], solve Maxwell's equations directly for cases of interest in IC and PCB design. They are known for being slower but more accurate than the [[layout extraction]] above.
* [[Physical verification]], PV: checking if a design is physically manufacturable, and that the resulting chips will not have any function-preventing physical defects, and will meet original specifications.