Editing Flash memory (section)

===Floating-gate MOSFET===
{{Main| Floating-gate MOSFET}}

In flash memory, each memory cell resembles a standard [[metal–oxide–semiconductor field-effect transistor]] (MOSFET) except that the transistor has two gates instead of one. The cells can be seen as an electrical switch in which current flows between two terminals (source and drain) and is controlled by a floating gate (FG) and a control gate (CG). The CG is similar to the gate in other MOS transistors, but below this is the FG, which is insulated all around by an oxide layer. The FG is interposed between the CG and the MOSFET channel. Because the FG is electrically isolated by its insulating layer, electrons placed on it are trapped. When the FG is charged with electrons, this charge [[electric field screening|screens]] the [[electric field]] from the CG, thus increasing the [[threshold voltage]] (V<sub>T</sub>) of the cell. This means that the V<sub>T</sub> of the cell can be changed between the ''uncharged FG threshold voltage'' (V<sub>T1</sub>) and the higher ''charged FG threshold voltage'' (V<sub>T2</sub>) by changing the FG charge. In order to read a value from the cell, an intermediate voltage (V<sub>I</sub>) between V<sub>T1</sub> and V<sub>T2</sub> is applied to the CG. If the channel conducts at V<sub>I</sub>, the FG must be uncharged (if it were charged, there would not be conduction because V<sub>I</sub> is less than V<sub>T2</sub>). If the channel does not conduct at the V<sub>I</sub>, it indicates that the FG is charged. The binary value of the cell is sensed by determining whether there is current flowing through the transistor when V<sub>I</sub> is asserted on the CG. In a multi-level cell device, which stores more than one [[bit]] per cell, the amount of current flow is sensed (rather than simply its presence or absence), in order to determine more precisely the level of charge on the FG.

Floating gate MOSFETs are so named because there is an electrically insulating tunnel oxide layer between the floating gate and the silicon, so the gate "floats" above the silicon. The oxide keeps the electrons confined to the floating gate. Degradation or wear (and the limited endurance of floating gate Flash memory) occurs due to the extremely high [[electric field]] (10 million volts per centimeter) experienced by the oxide. Such high voltage densities can break atomic bonds over time in the relatively thin oxide, gradually degrading its electrically insulating properties and allowing electrons to be trapped in and pass through freely (leak) from the floating gate into the oxide, increasing the likelihood of data loss since the electrons (the quantity of which is used to represent different charge levels, each assigned to a different combination of bits in MLC Flash) are normally in the floating gate. This is why data retention goes down and the risk of data loss increases with increasing degradation.<ref name="windbacher-211">{{Cite web |last=Windbacher |first=T. |title=2.1.1 Flash Memory |url=https://www.iue.tuwien.ac.at/phd/windbacher/node14.html |url-status=live |archive-url=https://web.archive.org/web/20231109113308/https://www.iue.tuwien.ac.at/phd/windbacher/node14.html |archive-date=9 November 2023 |website=Engineering Gate Stacks for Field-Effect Transistors }}</ref><ref name="minnesota-floating-gate-mos">{{Cite web |title=Floating Gate MOS Memory |url=http://www.princeton.edu/~chouweb/newproject/research/SEM/FloatMOSMem.html |url-status=dead |archive-url=https://web.archive.org/web/20220808223834/http://www.princeton.edu/~chouweb/newproject/research/SEM/FloatMOSMem.html |archive-date=8 August 2022 |publisher=[[University of Minnesota]] }}</ref><ref name="auto5"/><ref name="anandtech"/><ref name="electronics-notes-wear-levelling">{{Cite web |title=Flash Memory Reliability, Life & Wear |url=https://www.electronics-notes.com/articles/electronic_components/semiconductor-ic-memory/flash-wear-levelling-reliability-lifetime.php |url-status=live |archive-url=https://web.archive.org/web/20231102133652/https://www.electronics-notes.com/articles/electronic_components/semiconductor-ic-memory/flash-wear-levelling-reliability-lifetime.php |archive-date=2 November 2023 |website=Electronics Notes }}</ref> The silicon oxide in a cell degrades with every erase operation. The degradation increases the amount of negative charge in the cell over time due to trapped electrons in the oxide and negates some of the control gate voltage. Over time, this  also makes erasing the cell slower; to maintain the performance and reliability of the NAND chip, the cell must be retired from use.  Endurance also decreases with the number of bits in a cell. With more bits in a cell, the number of possible states (each represented by a different voltage level) in a cell increases and is more sensitive to the voltages used for programming. Voltages may be adjusted to compensate for degradation of the silicon oxide, and as the number of bits increases, the number of possible states also increases and thus the cell is less tolerant of adjustments to programming voltages, because there is less space between the voltage levels that define each state in a cell.<ref name="auto6">{{Cite news |last=Vättö |first=Kristian |date=23 February 2012 |title=Understanding TLC NAND |work=[[AnandTech]] |url=https://www.anandtech.com/show/5067/understanding-tlc-nand/2 |url-status=live |archive-url=https://web.archive.org/web/20231102131132/https://www.anandtech.com/show/5067/understanding-tlc-nand/2 |archive-date=2 November 2023 }}</ref>