Editing IBM System/360 (section)

==Technical description==
{{prose|section|date=November 2020}}

===Influential features===
[[Image:IBM 360 20 TROS.jpg|thumb|[[IBM System/360 Model 20]] [[microcode]] [[transformer read-only storage]] (TROS) module. A Model 40 (TROS) module is about 50% longer than this to make room for more microcode bits in the word.]]

The System/360 introduced a number of industry standards to the marketplace, such as:
* The [[8-bit computing|8-bit]] [[byte]] (against financial pressure during development to reduce the byte to 4 or 6 bits), rather than adopting the [[IBM 7030|7030]] concept of accessing bytes of variable size at arbitrary bit addresses.
* Byte-[[memory address|addressable]] memory (as opposed to bit-addressable or word-addressable memory)
* [[32-bit computing|32-bit]] [[integer (computer science)#Words|words]]
* The [[Bus and Tag]] I/O channel standardized in FIPS-60<ref>{{citation|id=FIPSPUB60|publisher=National Technical Information Service|title=I/O Channel Interface|author=NTIS|year=1979}}</ref>
* Commercial use of [[microcode]]d CPUs
* The [[IBM hexadecimal floating-point|IBM hexadecimal floating-point architecture]]<ref>{{Cite journal |title=Architecture and software support in IBM S/390 Parallel Enterprise Servers for IEEE Floating-Point arithmetic |date=1999 |doi=10.1147/rd.435.0723 |url=https://ieeexplore.ieee.org/document/5389154 |last1=Abbott |first1=P. H. |last2=Brush |first2=D. G. |last3=Clark |first3=C. W. |last4=Crone |first4=C. J. |last5=Ehrman |first5=J. R. |last6=Ewart |first6=G. W. |last7=Goodrich |first7=C. A. |last8=Hack |first8=M. |last9=Kapernick |first9=J. S. |last10=Minchau |first10=B. J. |last11=Shepard |first11=W. C. |last12=Smith |first12=R. M. |last13=Tallman |first13=R. |last14=Walkowiak |first14=S. |last15=Watanabe |first15=A. |last16=White |first16=W. R. |journal=IBM Journal of Research and Development |volume=43 |issue=5.6 |pages=723–760 |url-access=subscription }}</ref>
* The [[EBCDIC]] character set<ref group=NB>In System/360 architecture bit 12 of the [[program status word]] (PSW) controlled selection between the [[EBCDIC]] or a then proposed [[ASCII|ASCII-8]] mode signed decimal data. The proposed ASCII-8 [[ANSI]] standard was in the approval process when System/360 was announced but it was subsequently rejected and no ASCII peripheral devices were made available. This capability was not included in System/370; bit 12 of the PSW was redefined to switch between System/360 (BC mode) and System/370 (EC mode) PSW format.</ref>
* [[9-track tape|Nine-track magnetic tape]]

===Architectural overview===
{{Main|IBM System/360 architecture}}

The System/360 series [[computer architecture]] specification makes no assumptions on the implementation itself, but rather describes the interfaces and expected behavior of an implementation.<ref name=A22-6821/><ref name=A22-6821-8/><ref name=A22-6843/> The architecture describes mandatory interfaces that must be available on all implementations, and optional interfaces. Some aspects of this architecture are:
* [[Big endian]] byte ordering
* A processor with:
** 16 [[32-bit computing|32-bit]] [[general-purpose register]]s (R0–R15)
** A 64-bit [[program status word]] (PSW), which describes (among other things)
*** [[Interrupt]] masks
*** Privilege states
*** A condition code
*** A 24-bit [[program counter|instruction address]]
** An interruption mechanism, [[interrupt|maskable]] and unmaskable interruption classes and subclasses
** An [[instruction set]]. Each instruction is wholly described and also defines the conditions under which an exception is recognized in the form of program interruption.
* A [[primary storage|memory (called storage) subsystem]] with:
** 8 bits per byte
** A special processor communication area starting at address 0
** 24-bit addressing
* Manual control operations that allow
** A [[booting|bootstrap]] process (a process called Initial Program Load or IPL)
** Operator-initiated interrupts
** Resetting the system
** Basic debugging facilities
** Manual display and modifications of the system's state (memory and processor)
* An Input/Output mechanism{{snd}} which does not describe the devices themselves

Some of the optional features are:
* [[Binary-coded decimal]] instructions
* [[Floating-point arithmetic|Floating-point]] instructions
* Timing facilities (interval timer)
* [[Memory protection key|Key-controlled memory protection]]

All models of System/360, except for the Model 20 and Model 44, implemented that specification.

Binary arithmetic and logical operations are performed as register-to-register and as memory-to-register/register-to-memory as a standard feature. If the Commercial Instruction Set option was installed, [[Binary-coded decimal|packed decimal]] arithmetic could be performed as memory-to-memory with some memory-to-register operations. The Scientific Instruction Set feature, if installed, provided access to four [[floating-point arithmetic|floating-point]] registers that could be programmed for either [[32-bit computing|32-bit]] or [[64-bit computing|64-bit]] floating-point operations. The Models 85 and 195 could also operate on 128-bit extended-precision floating-point numbers stored in pairs of floating-point registers, and software provided emulation in other models. The System/360 used an 8-bit byte, 32-bit word, 64-bit double-word, and 4-bit [[nybble|nibble]]. Machine instructions had operators with operands, which could contain register numbers or memory addresses. This complex combination of instruction options resulted in a variety of instruction lengths and formats.

Memory addressing was accomplished using a base-plus-displacement scheme, with registers 1 through F (15). A displacement was encoded in 12 bits, thus allowing a 4096-byte displacement (0–4095), as the offset from the address put in a base register.

Register 0 could not be used as a base register nor as an index register (nor as a branch address register), as "0" was reserved to indicate an address in the first 4&nbsp;KB of memory, that is, if register 0 was specified as described, the value 0x00000000 was implicitly input to the effective address calculation in place of whatever value might be contained within register 0 (or if specified as a branch address register, then no branch was taken, and the content of register 0 was ignored, but any side effect of the instruction was performed).

This specific behavior permitted initial execution of an interrupt routines, since base registers would not necessarily be set to 0 during the first few instruction cycles of an interrupt routine. It isn't needed for [[Initial Program Load|IPL]] ("Initial Program Load" or boot), as one can always clear a register without the need to save it.

With the exception of the Model 67,<ref name=GA27-2719/> all addresses were real memory addresses. Virtual memory was not available in most IBM mainframes until the [[System/370]] series. The Model 67 introduced a virtual memory architecture, which [[Michigan Terminal System|MTS]], [[CP-67]], and [[TSS/360]] used—but not IBM's mainline System/360 operating systems.

The System/360 machine-code instructions are 2 bytes long (no memory operands), 4 bytes long (one operand), or 6 bytes long (two operands). Instructions are always situated on 2-byte boundaries.

Operations like MVC (Move-Characters) (Hex: D2) can only move at most 256 bytes of information. Moving more than 256 bytes of data required multiple MVC operations. (The [[System/370]] series introduced a family of more powerful instructions such as the MVCL "Move-Characters-Long" instruction, which supports moving up to 16&nbsp;MB as a single block.)

An operand is two bytes long, typically representing an address as a 4-bit [[nybble|nibble]] denoting a base register and a 12-bit displacement relative to the contents of that register, in the range {{mono|000–FFF}} (shown here as [[hexadecimal]] numbers). The address corresponding to that operand is the contents of the specified general-purpose register plus the displacement. For example, an MVC instruction that moves 256 bytes (with length code 255 in hexadecimal as {{mono|FF}}) from base register 7, plus displacement {{mono|000}}, to base register 8, plus displacement {{mono|001}}, would be coded as the 6-byte instruction "{{mono|D2FF 8001 7000}}" (operator/length/address1/address2).

The System/360 was designed to separate the ''system state'' from the ''problem state''. This provided a basic level of security and recoverability from programming errors. Problem (user) programs could not modify data or program storage associated with the system state. Addressing, data, or operation exception errors made the machine enter the system state through a controlled routine so the operating system could try to correct or terminate the program in error. Similarly, it could recover certain processor hardware errors through the ''machine check'' routines.

===Channels===
{{See also|Channel I/O}}

Peripherals interfaced to the system via ''channels''. A channel is a specialized processor with the instruction set optimized for transferring data between a peripheral and main memory. In modern terms, this could be compared to [[direct memory access]] (DMA). The S/360 connects channels to control units with [[Bus and Tag|bus and tag]] cables; IBM eventually replaced these with [[ESCON|Enterprise Systems Connection]] (ESCON) and [[FICON|Fibre Connection]] (FICON) channels, but well after the S/360 era.

===={{anchor|ByteMuxChan|SelectChan}}Byte-multiplexor and selector channels====<!-- anchor added for intra-article linking -->
There were initially two types of channels; byte-multiplexer channels (known at the time simply as "multiplexor channels"), for connecting "slow speed" devices such as card readers and punches, [[line printer]]s, and communications controllers, and selector channels for connecting high speed devices, such as [[disk drive]]s, [[tape drive]]s, data cells and [[drum memory|drums]]. Every System/360 (except for the Model 20, which was not a standard 360) has a byte-multiplexer channel and 1 or more selector channels, though the model 25 has just one channel, which can be either a byte-multiplexor or selector channel. The smaller models (up to the model 50) have integrated channels, while for the larger models (model 65 and above) the channels are large separate units in separate cabinets: the IBM 2870 is the byte-multiplexor channel with up to four selector sub-channels, and the IBM 2860 is up to three selector channels.

The byte-multiplexer channel is able to handle I/O to/from several devices simultaneously at the device's highest rated speeds, hence the name, as it [[multiplexing|multiplexed]] I/O from those devices onto a single data path to main memory. Devices connected to a byte-multiplexer channel are configured to operate in 1-byte, 2-byte, 4-byte, or "burst" mode. The larger "blocks" of data are used to handle progressively faster devices. For example, a 2501 card reader operating at 600 cards per minute would be in 1-byte mode, while a 1403-N1 printer would be in burst mode. Also, the byte-multiplexer channels on larger models have an optional selector subchannel section that would accommodate tape drives. The byte-multiplexor's channel address was typically "0" and the selector subchannel addresses were from "C0" to "FF." Thus, tape drives on System/360 were commonly addressed at 0C0–0C7. Other common byte-multiplexer addresses are: 00A: 2501 Card Reader, 00C/00D: 2540 Reader/Punch, 00E/00F: 1403-N1 Printers, 010–013: 3211 Printers, 020–0BF: [[270x|2701/2703]] Telecommunications Units. These addresses are still commonly used in z/VM virtual machines.

System/360 models 40 and 50 have an integrated 1052-7 console that is usually addressed as 01F, however, this was not connected to the byte-multiplexer channel, but rather, had a direct internal connection to the mainframe. The model 30 attached a different model of 1052 through a 1051 control unit. The models 60 through 75 also use the 1052–7.

[[File:IBM 360 Bus Tag Cables.png|thumb|300px|Cable used as Bus or Tag cable for IBM System/360]]
[[Image:IBM 360 Bus Tag Terms.JPG|thumb|300px|Bus and tag terminators]]

Selector channels enabled I/O to high speed devices. These storage devices were attached to a control unit and then to the channel. The control unit let clusters of devices be attached to the channels. On higher speed models, multiple selector channels, which could operate simultaneously or in parallel, improved overall performance.

Control units are connected to the channels with "bus and tag" cable pairs. The bus cables carried the address and data information and the tag cables identified what data was on the bus. The general configuration of a channel is to connect the devices in a chain, like this: Mainframe—Control Unit X—Control Unit Y—Control Unit Z. Each control unit is assigned a "capture range" of addresses that it services. For example, control unit X might capture addresses 40–4F, control unit Y: C0–DF, and control unit Z: 80–9F. Capture ranges had to be a multiple of 8, 16, 32, 64, or 128 devices and be aligned on appropriate boundaries. Each control unit in turn has one or more devices attached to it. For example, you could have control unit Y with 6 disks, that would be addressed as C0-C5.

There are three general types of bus-and-tag cables produced by IBM. The first is the standard gray bus-and-tag cable, followed by the blue bus-and-tag cable, and finally the tan bus-and-tag cable. Generally, newer cable revisions are capable of higher speeds or longer distances, and some peripherals specified minimum cable revisions both upstream and downstream.

The cable ordering of the control units on the channel is also significant. Each control unit is "strapped" as High or Low priority. When a device selection was sent out on a mainframe's channel, the selection was sent from X->Y->Z->Y->X. If the control unit was "high" then the selection was checked in the outbound direction, if "low" then the inbound direction. Thus, control unit X was either 1st or 5th, Y was either 2nd or 4th, and Z was 3rd in line. It is also possible to have multiple channels attached to a control unit from the same or multiple mainframes, thus providing a rich high-performance, multiple-access, and backup capability.

Typically the total cable length of a channel is limited to 200 feet, less being preferred. Each control unit accounts for about 10 "feet" of the 200-foot limit.

===={{anchor|BMuxChan}}Block multiplexer channel====
IBM first introduced a new type of I/O channel on the Model 85 and Model 195, the [[IBM 2880|2880]] block multiplexer channel, and then made them standard on the [[System/370]]. This channel allowed a device to suspend a channel program, pending the completion of an I/O operation and thus to free the channel for use by another device. A block multiplexer channel can support either standard 1.5&nbsp;MB/s connections or, with the 2-byte interface feature, 3&nbsp;MB/s; the latter use one tag cable and two bus cables. On the [[IBM System/370|S/370]] there is an option for a 3.0 MB/s data streaming<ref name=OEMI>{{cite book
 | title     = IBM System/360 and System/370 I/O Interface Channel to Control Unit Original Equipment Manufacturers' Information 
 | section   = Data-Streaming Feature
 | pages     = 3-4&ndash;3-7
 | edition   = Tenth
 | date      = February 1988
 | publisher = IBM
 | url       = http://bitsavers.org/pdf/ibm/370/channel/GA22-6974-9_360_370_IO_Interface_Channel_to_Control_Unit_OEM_Information_Feb88.pdf
 | mode      = cs2}}</ref> channel with one bus cable and one tag cable.

The initial use for this was the 2305 fixed-head disk, which has 8 "exposures" (alias addresses) and rotational position sensing (RPS).

Block multiplexer channels can operate as a selector channel to allow compatible attachment of legacy subsystems.<ref>{{cite book
 | title       = System/370 Principles of Operation
 | id          = GA22-7000-4
 | url         = http://www.bitsavers.org/pdf/ibm/370/princOps/GA22-7000-4_370_Principles_Of_Operation_Sep75.pdf
 | publisher   = IBM
 | date        = September 1975
 | page        = 189
 | access-date = December 30, 2015}}</ref>

===Basic hardware components===
[[File:IBM SLT card 03773.agr.jpg|thumb|A single-width [[Solid Logic Technology|SLT card]]. Each square metal can contains a [[hybrid circuit]] with several transistors.]]
[[File:IBM SLT chip, side view.jpg|thumb|upright|Six-transistor solid logic hybrid circuit with cap off]]
[[File:SLT Card Frame.corestore.jpg|thumb|upright|Many SLT cards plugged into an SLT backplane]]

Being uncertain of the reliability and availability of the then new monolithic [[integrated circuit]]s, IBM chose instead to design and manufacture its own custom [[hybrid integrated circuit]]s. These were built on 11&nbsp;mm square [[ceramic]] substrates. [[Resistor]]s were [[screen-printing|silk screened]] on and discrete [[glass]] encapsulated [[transistor]]s and [[diode]]s were added. The substrate was then covered with a metal lid or encapsulated in plastic to create a "[[Solid Logic Technology]]" (SLT) module.

A number of these [https://web.archive.org/web/20050122174353/http://www-03.ibm.com/ibm/history/exhibits/vintage/vintage_4506VV3081.html SLT modules] were then [[flip chip]] mounted onto a small multi-layer [[printed circuit board|printed circuit]] "SLT card". Each card had one or two sockets on one edge that plugged onto pins on one of the computer's "SLT boards" (also referred to as a backplane). This was the reverse of how most other company's cards were mounted, where the cards had pins or [[Edge connector|printed contact areas]] and plugged into sockets on the computer's boards.

Up to twenty SLT boards could be assembled side-by-side (vertically and horizontally, max 4 high by 5 wide) to form a "logic gate". Several gates mounted together constituted a box-shaped "logic frame". The outer gates were generally hinged along one vertical edge so they could be swung open to provide access to the fixed inner gates. The larger machines could have more than one frame bolted together to produce the final unit, such as a multi-frame Central Processing Unit (CPU).

===Operating system software===
{{Main|History of IBM mainframe operating systems#System/360 operating systems|l1=System/360 operating systems}}

The smaller System/360 models used the Basic Operating System/360 ([[BOS/360]]), Tape Operating System (TOS/360), or Disk Operating System/360 ([[DOS/360]], which evolved into DOS/VS, DOS/VSE, VSE/AF, VSE/SP, VSE/ESA, and then [[VSE (operating system)|z/VSE]]).

The larger models used [[OS/360 and successors|Operating System/360]] (OS/360). IBM developed several levels of OS/360, with increasingly powerful features: Primary Control Program (PCP), [[MFT (operating system)|Multiprogramming with a Fixed number of Tasks]] (MFT), and [[Multiprogramming with a Variable number of Tasks]] (MVT). MVT took a long time to develop into a usable system, and the less ambitious MFT was widely used. PCP was used on intermediate machines too small to run MFT well, and on larger machines before MFT was available; the final releases of OS/360 included only MFT and MVT.  For the [[System/370]] and later machines, MFT evolved into [[OS/VS1]], while MVT evolved into [[OS/VS2 (SVS)]] (Single Virtual Storage), then various versions of [[MVS]] (Multiple Virtual Storage) culminating in the current [[z/OS]].

When it announced the [[IBM System/360 Model 67|Model 67]] in August 1965, IBM also announced [[TSS/360]] (Time-Sharing System) for delivery at the same time as the 67. TSS/360, a response to [[Multics]], was an ambitious project that included many advanced features. It had performance problems, was delayed, canceled, reinstated, and finally canceled<ref group=NB>However, it could still be ordered, and a TSS/370 [[Request price quotation|PRPQ]] was available on the S/370 and went through multiple releases.</ref> again in 1971. Customers migrated to [[CP-67]], MTS ([[Michigan Terminal System]]), TSO ([[Time Sharing Option]] for OS/360), or one of several other [[time-sharing]] systems.

CP-67, the original [[virtual machine]] system, was also known as [[CP/CMS]]. CP/67 was developed outside the IBM mainstream at IBM's [[Cambridge Scientific Center]], in cooperation with [[MIT]] researchers. CP/CMS eventually won wide acceptance, and led to the development of [[VM/370]] (Virtual Machine) which had a primary interactive "sub" operating system known as [[VM/CMS]] (Conversational Monitoring System). This evolved into today's [[z/VM]].

The Model 20 offered a simplified and rarely used tape-based system called TPS (Tape Processing System), and DPS (Disk Processing System) that provided support for the 2311 disk drive. TPS could run on a machine with 8&nbsp;KB of memory; DPS required 12&nbsp;KB, which was pretty hefty for a Model 20. Many customers ran quite happily with 4&nbsp;KB and CPS (Card Processing System). With TPS and DPS, the card reader was used to read the [[Job Control Language]] cards that defined the stack of jobs to run and to read in transaction data such as customer payments. The operating system was held on tape or disk, and results could also be stored on the tapes or hard drives. Stacked job processing became an exciting possibility for the small but adventurous computer user.

A little-known and little-used suite of 80-column punched-card utility programs known as [[IBM Basic Programming Support|Basic Programming Support]] (BPS) (jocularly: Barely Programming Support), a precursor of TOS, was available for smaller systems.