Editing Instruction pipelining (section)

===Special situations===
; Self-modifying programs
: The technique of [[self-modifying code]] can be problematic on a pipelined processor. In this technique, one of the effects of a program is to modify its own upcoming instructions. If the processor has an [[instruction cache]], the original instruction may already have been copied into a [[prefetch input queue]] and the modification will not take effect. Some processors such as the [[Zilog Z280]] can configure their on-chip cache memories for data-only fetches, or as part of their ordinary memory address space, and avoid such difficulties with self-modifying instructions.

; Uninterruptible instructions
: An instruction may be uninterruptible to ensure its [[atomicity (programming)|atomicity]], such as when it swaps two items. A sequential processor permits [[interrupt]]s between instructions, but a pipelining processor overlaps instructions, so executing an uninterruptible instruction renders portions of ordinary instructions uninterruptible too. The [[Cyrix coma bug]] would [[hang (computing)|hang]] a single-core system using an infinite loop in which an uninterruptible instruction was always in the pipeline.