Editing Intel i960 (section)

===80960MX===
The 80960MX is a superscalar implementation of the Extended architecture, executing up to three instructions per clock execution for sustained performance of 25 VAX MIPS.<ref name="intel-military">{{cite book |title=Military and Special Products Handbook |date=1993 |publisher=Intel |pages=11-40 to 11-89 |chapter=i960 MX Processor}}</ref> It implemented the Joint Industrial Avionics Working Group (JIAWG) 32-bit ISA standard. It was originally packaged in a 348 lead ceramic pin grid array and later supplied as a bare die. The i960 MX supports object-oriented programming. A 33rd tag bit distinguished between a 32-bit data word and a 32-bit pointer to memory. This prohibited forged pointers to protected areas of memory.