Editing Itanium (section)

=== Itanium 2 9000 and Itanium 9100: 2006 and 2007 ===
{{Infobox CPU
 | name=9000 and 9100 series
 | image=Intel Itanium 2 9000 with cap removed.jpg
 | image_size=300px
 | caption=Intel Itanium&nbsp;2 9000 ([[heat spreader]] [[Decapping|removed]])
 | produced-start=18 July 2006
 | produced-end=26 August 2011<ref>{{cite web |title=Intel server processors to be discontinued in 2012 |url=https://www.cpu-world.com/news_2011/2011021601_Intel_server_processors_to_be_discontinued_in_2012.html |website=CPU-World |access-date=28 April 2022}}</ref>
 | slowest=1.4
 | fastest=1.67
 | fast-unit=GHz
 | fsb-slowest=400
 | fsb-fastest=667
 | fsb-slow-unit=
 | fsb-fast-unit=MT/s
 | hypertransport-slowest=
 | hypertransport-fastest=
 | hypertransport-slow-unit=
 | hypertransport-fast-unit=
 | size-from=[[90 nm]]
 | size-to=
 | soldby=
 | designfirm=
 | manuf1=
 | core1=
 | sock1=[[PAC611]]
 | pack1=
 | brand1=
 | arch=
 | microarch=
 | cpuid=
 | code=Montecito, Montvale
 | numcores=1 or 2
 | l1cache=
 | l2cache=256&nbsp;KB&nbsp;(D) + 1&nbsp;MB&nbsp;(I)
 | l3cache=6–24&nbsp;MB
 | application=
}}
{{Main|Montecito (processor)}}
In early 2003, due to the success of IBM's dual-core [[POWER4]], Intel announced that the first [[90 nm]] Itanium processor, codenamed ''Montecito'', would be delayed to 2005 so as to change it into a dual-core, thus merging it with the ''Chivano'' project.<ref>{{cite web |last1=Kanellos |first1=Michael |title=Intel accelerates Itanium schedule |url=https://www.cnet.com/tech/tech-industry/intel-accelerates-itanium-schedule/ |website=[[CNET]] |access-date=3 April 2022}}</ref><ref name="qa">{{cite news |last1=Shankland |first1=Stephen |last2=Kanellos |first2=Michael |title=Intel's summer of servers |url=https://www.theglobeandmail.com/technology/intels-summer-of-servers/article1163609/ |website=[[The Globe and Mail]] |date=9 July 2003 |access-date=27 April 2022}}</ref> In September 2004 Intel demonstrated a working Montecito system, and claimed that the inclusion of [[hyper-threading]] increases Montecito's performance by 10-20% and that its frequency could reach 2&nbsp;GHz.<ref name="monty">{{cite web |last1=Kanellos |first1=Michael |title=Intel fills in more details on Itanium family |url=https://www.cnet.com/tech/tech-industry/intel-fills-in-more-details-on-itanium-family/ |website=[[CNET]] |access-date=3 April 2022}}</ref><ref>{{cite web |last1=Wilson |first1=Derek |title=Intel Developer Forum Fall 2004: Day 1 Keynote |url=https://www.anandtech.com/show/1465/3 |website=[[AnandTech]] |access-date=28 April 2022}}</ref> After a delay to "mid-2006" and reduction of the frequency to 1.6&nbsp;GHz,<ref>{{cite news |last1=Shankland |first1=Stephen |title=Intel pushes back Itanium chips, revamps Xeon |url=https://www.cnet.com/tech/tech-industry/intel-pushes-back-itanium-chips-revamps-xeon/ |website=[[CNET]] |access-date=3 April 2022}}</ref> on July 18 Intel delivered ''Montecito'' (marketed as the '''Itanium&nbsp;2 9000''' series), a [[multi-core processor|dual-core]] processor with a [[Multithreading (computer architecture)#Coarse-grained multithreading|switch-on-event multithreading]] and split 256 KB + 1 MB L2 caches that roughly doubled the performance and decreased the energy consumption by about 20 percent.<ref name="CW1">{{cite web
 |url          = https://www.computerworld.com/article/2536018/-tukwila--itanium-servers-due-early-next-year--intel-says.html
 |title        = 'Tukwila' Itanium servers due early next year, Intel says
 |access-date  = September 26, 2022
 |last         = Niccolai
 |first        = James
 |date         = May 20, 2008
 |work         = [[Computerworld]]
}}</ref> At 596&nbsp;mm² die size and 1.72 billion transistors it was the largest microprocessor at the time. It was supposed to feature [[Foxton Technology]], a very sophisticated frequency regulator, which failed to pass validation and was thus not enabled for customers.

Intel released the '''Itanium 9100''' series, codenamed ''Montvale'', in November 2007, retiring the "Itanium 2" brand.<ref name="IW1">{{cite web
 | url=http://www.informationweek.com/story/showArticle.jhtml?articleID=202800983
 | title=Intel Unveils Seven Itanium Processors
 | access-date=November 6, 2007
 | last=Gonsalves
 | first=Antone
 | date=November 1, 2007
 | work=[[InformationWeek]]
 | archive-date=March 10, 2012
 | archive-url=https://web.archive.org/web/20120310003352/http://www.informationweek.com/
 | url-status=dead
 }}</ref> Originally intended to use the [[65 nm process]],<ref name="idf04f">{{cite web |title=Intel Shares Findings, Platform Plans To Better Guide Businesses Through 'Transformation' |url=https://www.intel.com/pressroom/archive/releases/2004/20040907corp_a.htm |publisher=Intel}}</ref> it was changed into a fix of Montecito, enabling the demand-based switching (like [[EIST]]) and up to 667 MT/s [[front-side bus]], which were intended for Montecito, plus a core-level [[Lockstep (computing)|lockstep]].<ref name="monty"/> Montecito and Montvale were the last Itanium processors in which design [[Hewlett-Packard]]'s engineering team at Fort Collins had a key role, as the team was subsequently transferred to Intel's ownership.<ref>{{cite web |title=Intel Strengthens Investment In Intel® Itanium® Architecture With Hiring Of HP Design Team |url=https://www.intel.com/pressroom/archive/releases/2004/20041216comp.htm}}</ref>