Editing Microarchitecture (section)

=== Instruction pipelining ===
{{Main|Instruction pipelining}}

One of the first, and most powerful, techniques to improve performance is the use of [[instruction pipelining]]. Early processor designs would carry out all of the steps above for one instruction before moving onto the next. Large portions of the circuitry were left idle at any one step; for instance, the instruction decoding circuitry would be idle during execution and so on.

Pipelining improves performance by allowing a number of instructions to work their way through the processor at the same time. In the same basic example, the processor would start to decode (step 1) a new instruction while the last one was waiting for results. This would allow up to four instructions to be "in flight" at one time, making the processor look four times as fast. Although any one instruction takes just as long to complete (there are still four steps) the CPU as a whole "retires" instructions much faster.

RISC makes pipelines smaller and much easier to construct by cleanly separating each stage of the instruction process and making them take the same amount of time—one cycle. The processor as a whole operates in an [[assembly line]] fashion, with instructions coming in one side and results out the other. Due to the reduced complexity of the [[classic RISC pipeline]], the pipelined core and an instruction cache could be placed on the same size die that would otherwise fit the core alone on a CISC design. This was the real reason that RISC was faster. Early designs like the [[SPARC]] and [[MIPS architecture|MIPS]] often ran over 10 times as fast as [[Intel]] and [[Motorola]] CISC solutions at the same clock speed and price.

Pipelines are by no means limited to RISC designs. By 1986 the top-of-the-line VAX implementation ([[VAX 8000|VAX 8800]]) was a heavily pipelined design, slightly predating the first commercial MIPS and SPARC designs. Most modern CPUs (even embedded CPUs) are now pipelined, and microcoded CPUs with no pipelining are seen only in the most area-constrained embedded processors.{{Example needed |s|date=December 2018}} Large CISC machines, from the VAX 8800 to the modern Intel and AMD processors, are implemented with both microcode and pipelines. Improvements in pipelining and caching are the two major microarchitectural advances that have enabled processor performance to keep pace with the circuit technology on which they are based.