Editing PCI Express (section)

==== Pinout ====
The following table identifies the conductors on each side of the [[edge connector]] on a PCI Express card. The solder side of the [[printed circuit board]] (PCB) is the A-side, and the component side is the B-side.<ref name="IM1RH" /> PRSNT1# and PRSNT2# pins must be slightly shorter than the rest, to ensure that a hot-plugged card is fully inserted. The WAKE# pin uses full voltage to wake the computer, but must be [[pull up resistor|pulled high]] from the standby power to indicate that the card is wake capable.<ref name="PCIe card 2" />

{| class="wikitable"
|+ PCI Express connector pinout (x1, x4, x8 and x16 variants)
! Pin !! Side B !! Side A !! Description
| rowspan=54 |
! Pin !! Side B !! Side A !! Description
|-
! {{0}}1
|style="background:silver"| +12&nbsp;V || style="background:#9f9"| PRSNT1# ||align="left"| Must connect to farthest PRSNT2# pin
! 50
|style="background:#99f"| HSOp(8) ||style="background:#ff9"| Reserved || rowspan="2" style="text-align:left;"| Lane 8 transmit data, + and −
|-
! {{0}}2
|style="background:silver"| +12&nbsp;V ||style="background:silver"| +12&nbsp;V || rowspan="2" style="text-align:left;"|Main power pins
! 51
|style="background:#99f"| HSOn(8) ||style="background:#999"| Ground
|-
! {{0}}3
|style="background:silver"| +12&nbsp;V ||style="background:silver"| +12&nbsp;V
! 52
|style="background:#999"| Ground ||style="background:#f9f"| HSIp(8) || rowspan="2" style="text-align:left;"| Lane 8 receive data, + and −
|-
! {{0}}4
|style="background:#999"| Ground ||style="background:#999"| Ground ||
! 53
|style="background:#999"| Ground ||style="background:#f9f"| HSIn(8)
|-
! {{0}}5
|style="background:#fc6"| SMCLK ||style="background:#99f"| TCK || rowspan="5" style="text-align:left;"| [[SMBus]] and [[JTAG]] port pins
! 54
|style="background:#99f"| HSOp(9) ||style="background:#999"| Ground || rowspan="2" style="text-align:left;"| Lane 9 transmit data, + and −
|-
! {{0}}6
|style="background:#fc6"| SMDAT ||style="background:#99f"| TDI
! 55
|style="background:#99f"| HSOn(9) ||style="background:#999"| Ground
|-
! {{0}}7
|style="background:#999"| Ground ||style="background:#f9f"| TDO
! 56
|style="background:#999"| Ground ||style="background:#f9f"| HSIp(9) || rowspan="2" style="text-align:left;"| Lane 9 receive data, + and −
|-
! {{0}}8
|style="background:silver"| +3.3&nbsp;V ||style="background:#99f"| TMS
! 57
|style="background:#999"| Ground ||style="background:#f9f"| HSIn(9)
|-
! {{0}}9
|style="background:#99f"| TRST# ||style="background:silver"| +3.3&nbsp;V
! 58
|style="background:#99f"| HSOp(10) ||style="background:#999"| Ground || rowspan="2" style="text-align:left;"| Lane 10 transmit data, + and −
|-
! 10
|style="background:silver"|+3.3&nbsp;V aux ||style="background:silver"| +3.3&nbsp;V ||align="left"| Aux power & [[Standby power]]
! 59
|style="background:#99f"| HSOn(10) ||style="background:#999"| Ground
|-
! 11
|style="background:#fc6"| WAKE# ||style="background:#fc6"| PERST# ||align="left"| Link reactivation; fundamental reset <ref name="ajnim" />
! 60
|style="background:#999"| Ground ||style="background:#f9f"| HSIp(10) || rowspan="2" style="text-align:left;"| Lane 10 receive data, + and −
|-
!colspan=4| Key notch
! 61
|style="background:#999"| Ground ||style="background:#f9f"| HSIn(10)
|-
! 12
|style="background:#f9f"| CLKREQ#<ref name="vj2hg" /> ||style="background:#999"| Ground ||align="left"| Clock Request Signal
! 62
|style="background:#99f"| HSOp(11) ||style="background:#999"| Ground || rowspan="2" style="text-align:left;"| Lane 11 transmit data, + and −
|-
! 13
|style="background:#999"| Ground ||style="background:#99f"| REFCLK+ ||align="left"| Reference clock differential pair
! 63
|style="background:#99f"| HSOn(11) ||style="background:#999"| Ground
|-
! 14
|style="background:#99f"| HSOp(0) ||style="background:#99f"| REFCLK− || rowspan="2" style="text-align:left;"| Lane 0 transmit data, + and −
! 64
|style="background:#999"| Ground ||style="background:#f9f"| HSIp(11) || rowspan="2" style="text-align:left;"| Lane 11 receive data, + and −
|-
! 15
|style="background:#99f"| HSOn(0) ||style="background:#999"| Ground
! 65
|style="background:#999"| Ground ||style="background:#f9f"| HSIn(11)
|-
! 16
|style="background:#999"| Ground ||style="background:#f9f"| HSIp(0) || rowspan="2" style="text-align:left;"| Lane 0 receive data, + and −
! 66
|style="background:#99f"| HSOp(12) ||style="background:#999"| Ground || rowspan="2" style="text-align:left;"| Lane 12 transmit data, + and −
|-
! 17
|style="background:#9f9"| PRSNT2# ||style="background:#f9f"| HSIn(0)
! 67
|style="background:#99f"| HSOn(12) ||style="background:#999"| Ground
|-
! 18
|style="background:#999"| Ground ||style="background:#999"| Ground ||
! 68
|style="background:#999"| Ground ||style="background:#f9f"| HSIp(12) || rowspan="2" style="text-align:left;"| Lane 12 receive data, + and −
|-
|colspan=4| PCI Express x1 cards end at pin 18
! 69
|style="background:#999"| Ground ||style="background:#f9f"| HSIn(12)
|-
! 19
|style="background:#99f"| HSOp(1) ||style="background:#ff9"| Reserved || rowspan="2" style="text-align:left;"| Lane 1 transmit data, + and −
! 70
|style="background:#99f"| HSOp(13) ||style="background:#999"| Ground || rowspan="2" style="text-align:left;"| Lane 13 transmit data, + and −
|-
! 20
|style="background:#99f"| HSOn(1) ||style="background:#999"| Ground
! 71
|style="background:#99f"| HSOn(13) ||style="background:#999"| Ground
|-
! 21
|style="background:#999"| Ground ||style="background:#f9f"| HSIp(1) || rowspan="2" style="text-align:left;"| Lane 1 receive data, + and −
! 72
|style="background:#999"| Ground ||style="background:#f9f"| HSIp(13) || rowspan="2" style="text-align:left;"| Lane 13 receive data, + and −
|-
! 22
|style="background:#999"| Ground ||style="background:#f9f"| HSIn(1)
! 73
|style="background:#999"| Ground ||style="background:#f9f"| HSIn(13)
|-
! 23
|style="background:#99f"| HSOp(2) ||style="background:#999"| Ground || rowspan="2" style="text-align:left;"| Lane 2 transmit data, + and −
! 74
|style="background:#99f"| HSOp(14) ||style="background:#999"| Ground || rowspan="2" style="text-align:left;"| Lane 14 transmit data, + and −
|-
! 24
|style="background:#99f"| HSOn(2) ||style="background:#999"| Ground
! 75
|style="background:#99f"| HSOn(14) ||style="background:#999"| Ground
|-
! 25
|style="background:#999"| Ground ||style="background:#f9f"| HSIp(2) || rowspan="2" style="text-align:left;"| Lane 2 receive data, + and −
! 76
|style="background:#999"| Ground ||style="background:#f9f"| HSIp(14) || rowspan="2" style="text-align:left;"| Lane 14 receive data, + and −
|-
! 26
|style="background:#999"| Ground ||style="background:#f9f"| HSIn(2)
! 77
|style="background:#999"| Ground ||style="background:#f9f"| HSIn(14)
|-
! 27
|style="background:#99f"| HSOp(3) ||style="background:#999"| Ground || rowspan="2" style="text-align:left;"| Lane 3 transmit data, + and −
! 78
|style="background:#99f"| HSOp(15) ||style="background:#999"| Ground || rowspan="2" style="text-align:left;"| Lane 15 transmit data, + and −
|-
! 28
|style="background:#99f"| HSOn(3) ||style="background:#999"| Ground
! 79
|style="background:#99f"| HSOn(15) ||style="background:#999"| Ground
|-
! 29
|style="background:#999"| Ground ||style="background:#f9f"| HSIp(3) || rowspan="2" style="text-align:left;"| Lane 3 receive data, + and −<br />"Power brake", active-low to reduce device power
! 80
|style="background:#999"| Ground ||style="background:#f9f"| HSIp(15) || rowspan="2" style="text-align:left;"| Lane 15 receive data, + and −
|-
! 30
|style="background:#fc6"| PWRBRK#<ref name="YpQVq" /> ||style="background:#f9f"| HSIn(3)
! 81
|style="background:#9f9"| PRSNT2# ||style="background:#f9f"| HSIn(15)
|-
! 31
|style="background:#9f9"| PRSNT2# ||style="background:#999"| Ground ||rowspan=2|
! 82
|style="background:#ff9"| Reserved ||style="background:#999"| Ground ||
|-
! 32
|style="background:#999"| Ground ||style="background:#ff9"| Reserved
|-
|colspan=4| PCI Express x4 cards end at pin 32
|-
! 33
|style="background:#99f"| HSOp(4) ||style="background:#ff9"| Reserved || rowspan="2" style="text-align:left;"| Lane 4 transmit data, + and −
|-
! 34
|style="background:#99f"| HSOn(4) ||style="background:#999"| Ground
|-
! 35
|style="background:#999"| Ground ||style="background:#f9f"| HSIp(4) || rowspan="2" style="text-align:left;"| Lane 4 receive data, + and −
|-
! 36
|style="background:#999"| Ground ||style="background:#f9f"| HSIn(4)
|-
! 37
|style="background:#99f"| HSOp(5) ||style="background:#999"| Ground || rowspan="2" style="text-align:left;"| Lane 5 transmit data, + and −
|-
! 38
|style="background:#99f"| HSOn(5) ||style="background:#999"| Ground
|-
! 39
|style="background:#999"| Ground ||style="background:#f9f"| HSIp(5) || rowspan="2" style="text-align:left;"| Lane 5 receive data, + and −
|-
! 40
|style="background:#999"| Ground ||style="background:#f9f"| HSIn(5)
|-
! 41
|style="background:#99f"| HSOp(6) ||style="background:#999"| Ground || rowspan="2" style="text-align:left;"| Lane 6 transmit data, + and −
|-
! 42
|style="background:#99f"| HSOn(6) ||style="background:#999"| Ground
|-
! 43
|style="background:#999"| Ground ||style="background:#f9f"| HSIp(6) || rowspan="2" style="text-align:left;"| Lane 6 receive data, + and −
!colspan=4| Legend
|-
! 44
|style="background:#999"| Ground ||style="background:#f9f"| HSIn(6)
!style="background:#999" colspan=2| Ground pin
| colspan="2" style="text-align:left;"| Zero volt reference
|-
! 45
|style="background:#99f"| HSOp(7) ||style="background:#999"| Ground || rowspan="2" style="text-align:left;"| Lane 7 transmit data, + and −
!style="background:silver" colspan=2| Power pin
| colspan="2" style="text-align:left;"| Supplies power to the PCIe card
|-
! 46
|style="background:#99f"| HSOn(7) ||style="background:#999"| Ground
!style="background:#f9f" colspan=2| Card-to-host pin
| colspan="2" style="text-align:left;"| Signal from the card to the motherboard
|-
! 47
|style="background:#999"| Ground ||style="background:#f9f"| HSIp(7) || rowspan="2" style="text-align:left;"| Lane 7 receive data, + and −
!style="background:#99f" colspan=2| Host-to-card pin
| colspan="2" style="text-align:left;"| Signal from the motherboard to the card
|-
! 48
|style="background:#9f9"| PRSNT2# ||style="background:#f9f"| HSIn(7)
!style="background:#fc6" colspan=2| [[Open drain]]
| colspan="2" style="text-align:left;"| May be pulled low or sensed by multiple cards
|-
! 49
|style="background:#999"| Ground ||style="background:#999"| Ground ||
!style="background:#9f9" colspan=2| Sense pin
| colspan="2" style="text-align:left;"| Tied together on card
|-
|colspan=4| PCI Express x8 cards end at pin 49
!style="background:#ff9" colspan=2| Reserved
| colspan="2" style="text-align:left;"| Not presently used, do not connect
|}