Editing PIC microcontrollers (section)

===PIC18===
{{Further|topic=this family of microcontrollers|PIC instruction listings#PIC18 high end core devices (16 bit)}}
In 2000, Microchip introduced the PIC18 architecture. Unlike the PIC17 series, it has proven to be very popular, with a large number of device variants presently in manufacture. In contrast to earlier devices, which were more often than not programmed in [[assembly language]], [[C programming language|C]] has become the predominant development language.<ref>{{cite web|url=http://www.microchipc.com/sourcecode/|title=Microchip PIC micros and C - source and sample code|website=www.microchipc.com|access-date=7 April 2018}}</ref>

The PIC18 series inherits most of the features and instructions of the PIC17 series, while adding a number of important new features:

* call stack is 21 bits wide and much deeper (31 levels deep)
* the call stack may be read and written (TOSU:TOSH:TOSL registers)
* conditional branch instructions
* indexed addressing mode (PLUSW)
* the FSR registers are extended to 12 bits, allowing them to linearly address the entire data address space
* the addition of another FSR register (bringing the number up to 3)

The RAM space is 12&nbsp;bits, addressed using a 4-bit bank select register (BSR) and an 8-bit offset in each instruction. An additional "access" bit in each instruction selects between bank 0 (''a''=0) and the bank selected by the BSR (''a''=1).

A 1-level stack is also available for the STATUS, WREG and BSR registers. They are saved on every interrupt, and may be restored on return. If interrupts are disabled, they may also be used on subroutine call/return by setting the ''s'' bit (appending ", FAST" to the instruction).

The auto increment/decrement feature was improved by removing the control bits and adding four new indirect registers per FSR. Depending on which indirect file register is being accessed, it is possible to postdecrement, postincrement, or preincrement FSR; or form the effective address by adding W to FSR.

In more advanced PIC18 devices, an "extended mode" is available which makes the addressing even more favorable to compiled code:

* a new offset addressing mode; some addresses which were relative to the access bank are now interpreted relative to the FSR2 register
* the addition of several new instructions, notably for manipulating the FSR registers.

PIC18 devices are still developed (2021) and fitted with CIP (Core Independent Peripherals)