Editing Physical Address Extension (section)

=== Summary of 32-bit paging===
In all page table formats supported by [[IA-32]] and [[x86-64]], the 12 least significant bits of the page table entry are either interpreted by the memory management unit or are reserved for operating system use. In processors that implement the "no-execute" or "execution disable" feature, the most significant bit (bit&nbsp;63) is the [[NX bit]]. The next eleven most significant bits (bits 52 through 62) are reserved for operating system use by both Intel and AMD's architecture specifications. Thus, from 64 bits in the page table entry, 12 low-order and 12 high-order bits have other uses, leaving 40 bits (bits 12 though 51) for the physical page number. Combined with 12 bits of "offset within page" from the linear address, a maximum of 52&nbsp;bits are available to address physical memory. This allows a maximum RAM configuration of 2<sup>52</sup>&nbsp;bytes, or 4&nbsp;petabytes (about 4.5×10<sup>15</sup> bytes).