Editing PowerPC (section)

== Implementations ==
[[File:IBM PPC604e 200.jpg|thumb|IBM [[PowerPC 600#PowerPC 604e|PowerPC 604e]] 200 MHz]]
[[File:broadwaycpu.JPG|thumb|Custom PowerPC CPU from the [[Wii]] video game console]]
[[File:XPC855TZP66D4 3K20A.jpg|thumb|The Freescale XPC855T Service Processor of a [[Sun Fire]] V20z]]

The first implementation of the architecture was the [[PowerPC 601]], released in 1992, based on the RSC, implementing a hybrid of the [[POWER1]] and PowerPC instructions. This allowed the chip to be used by IBM in their existing POWER1-based platforms, although it also meant some slight pain when switching to the 2nd generation "pure" PowerPC designs. Apple continued work on a new line of Macintosh computers based on the chip, and eventually released them as the 601-based ''[[Power Macintosh]]'' on March 14, 1994.

Accelerator cards based on the first-generation PowerPC chips were created for the [[Amiga]] in anticipation for a move to a possible new Amiga platform designed around the PowerPC. The accelerator cards also included either a [[Motorola 68040]] or [[Motorola 68060|68060]] CPU in order to maintain backwards compatibility, as very few apps at the time could run natively on the PPC chips. However, the new machines never materialized, and Commodore subsequently declared bankruptcy. Over a decade later, [[AmigaOS 4]] would be released, which would put the platform permanently on the architecture. OS4 is compatible with those first-generation accelerators, as well as several custom motherboards created for a new incarnation of the Amiga platform.

IBM also had a full line of PowerPC based desktops built and ready to ship; unfortunately, the operating system that IBM had intended to run on these desktops—[[Microsoft]] [[Windows NT]]—was not complete by early 1993, when the machines were ready for marketing. Accordingly, and further because IBM had developed animosity toward Microsoft, IBM decided to port [[OS/2]] to the PowerPC in the form of Workplace OS. This new software platform spent three years (1992 to 1995) in development and was canceled with the December 1995 developer release, because of the disappointing launch of the PowerPC 620. For this reason, the IBM PowerPC desktops did not ship, although the reference design (codenamed Sandalbow) based on the PowerPC 601 CPU was released as an RS/6000 model (''[[Byte (magazine)|Byte]]''{{'}}s April 1994 issue included an extensive article about the Apple and IBM PowerPC desktops).

Apple, which also lacked a PowerPC based OS, took a different route. Utilizing the portability platform yielded by the secret [[Star Trek project]], the company ported the essential pieces of their [[Classic Mac OS|Mac OS]] operating system to the PowerPC architecture, and further wrote a [[Mac 68k emulator|68k emulator]] that could run [[Motorola 68000 family|68k]] based applications and the parts of the OS that had not been rewritten.

The second generation was "pure" and includes the "low end" [[PowerPC 603]] and "high end" [[PowerPC 604]]. The 603 is notable due to its very low cost and power consumption. This was a deliberate design goal on Motorola's part, who used the 603 project to build the basic core for all future generations of PPC chips. Apple tried to use the 603 in a new laptop design but was unable due to the small 8&nbsp;[[Kilobyte|KB]] level 1 cache. The 68000 emulator in the Mac OS could not fit in 8&nbsp;KB and thus slowed the computer drastically.<ref>{{cite journal|url=https://pdfs.semanticscholar.org/9492/040bfd1226a08b25c92539fe4d724d01a5dc.pdf|archive-url=https://web.archive.org/web/20180730110252/https://pdfs.semanticscholar.org/9492/040bfd1226a08b25c92539fe4d724d01a5dc.pdf|url-status=dead|archive-date=July 30, 2018|title=Arthur Revitalizes PowerPC Line|author=Linley Gwennap|journal=[[Microprocessor Report]]|volume=11|issue=2|date=February 27, 1997|s2cid=51808955|quote=The 603’s tiny 8K caches were notoriously poor for Mac OS software, particularly for 68K emulation; even the 603e’s caches cause a significant performance hit at higher clock speeds. Given Arthur’s design target of 250 MHz and up, doubling the caches again made sense.}}</ref><ref>{{cite web |url=http://lowendmac.com/2014/cpus-powerpc-603-and-603e/ |title=CPUs: PowerPC 603 and 603e |last=Jansen |first=Daniel |date=2014 |publisher=Low End Mac |access-date=29 July 2018 |archive-date=October 30, 2018 |archive-url=https://web.archive.org/web/20181030054318/http://lowendmac.com/2014/cpus-powerpc-603-and-603e/ |url-status=live }}</ref> The [[PowerPC 600#PowerPC 603e and 603ev|603e]] solved this problem by having a 16&nbsp;KB [[CPU cache|L1 cache]], which allowed the emulator to run efficiently.

In 1993, developers at IBM's [[Essex Junction, Vermont|Essex Junction, Burlington, Vermont]] facility started to work on a version of the PowerPC that would support the Intel [[x86]] instruction set directly on the CPU. While this was just one of several concurrent power architecture projects that IBM was working on, this chip began to be known inside IBM and by the media as the [[PowerPC 600#PowerPC 615|PowerPC 615]]. Profitability concerns and rumors of performance issues in the switching between the x86 and native PowerPC instruction sets resulted in the project being canceled in 1995 after only a limited number of chips were produced for in-house testing. Aside the rumors, the switching process took only 5 cycles, or the amount of time needed for the processor to empty its instruction pipeline. Microsoft also aided the processor's demise by refusing to support the PowerPC mode.<ref>{{cite web|url=https://www.theregister.co.uk/1998/10/01/microsoft_killed_the_powerpc/|title=Microsoft killed the PowerPC 615|website=The Register|date=October 1, 1998|access-date=August 16, 2009|url-status=live|archive-url=https://web.archive.org/web/20090207090933/http://www.theregister.co.uk/1998/10/01/microsoft_killed_the_powerpc/|archive-date=February 7, 2009|df=mdy-all}}</ref>

The first 64-bit implementation is the [[PowerPC 620]], but it appears to have seen little use because Apple didn't want to buy it and because, with its large die area, it was too costly for the embedded market. It was later and slower than promised, and IBM used their own [[POWER3]] design instead, offering no 64-bit "small" version until the late-2002 introduction of the [[PowerPC 970]]. The 970 is a 64-bit processor derived from the [[POWER4]] server processor. To create it, the POWER4 core was modified to be backward-compatible with 32-bit PowerPC processors, and a vector unit (similar to the [[AltiVec]] extensions in Motorola's 74xx series) was added.

IBM's [[IBM RS64|RS64]] processors are a family of chips implementing the "Amazon" variant of the PowerPC architecture. These processors are used in the [[RS/6000]] and [[IBM AS/400]] computer families; the Amazon architecture includes proprietary extensions used by AS/400.<ref>{{cite magazine|url=http://iprodeveloper.com/systems-management/inside-powerpc|title=Inside the PowerPC AS|date=July 1, 1995|author1=Adam T. Stallman|author2=Frank G. Soltis|magazine=System iNEWS Magazine|archive-url=https://web.archive.org/web/20130831203807/http://iprodeveloper.com/systems-management/inside-powerpc|archive-date=August 31, 2013}}</ref> The POWER4 and later POWER processors implement the Amazon architecture and replaced the RS64 chips in the RS/6000 and AS/400 families.

IBM developed a separate product line called the "4xx" line focused on the embedded market. These designs included the 401, 403, 405, 440, and 460. In 2004, IBM sold their 4xx product line to Applied Micro Circuits Corporation (AMCC). AMCC continues to develop new high performance products, partly based on IBM's technology, along with technology that was developed within AMCC. These products focus on a variety of applications including networking, wireless, storage, printing/imaging and industrial automation.

Numerically, the PowerPC is mostly found in controllers in cars. For the automotive market, Freescale Semiconductor initially offered many variations called the [[Mpc5xx|MPC5xx]] family such as the MPC555, built on a variation of the 601 core called the 8xx and designed in Israel by MSIL (Motorola Silicon Israel Limited). The 601 core is single issue, meaning it can only issue one instruction in a clock cycle. To this they add various bits of custom hardware, to allow for I/O on the one chip. In 2004, the next-generation four-digit [[PowerPC 5000#MPC55xx|55xx]] devices were launched for the automotive market. These use the newer [[PowerPC e200|e200]] series of PowerPC cores.

Networking is another area where embedded PowerPC processors are found in large numbers. MSIL took the [[QUICC]] engine from the [[Freescale 683XX|MC68302]] and made the [[PowerQUICC]] MPC860. This was a very famous processor used in many [[Cisco Systems|Cisco]] edge routers in the late 1990s. Variants of the PowerQUICC include the MPC850, and the MPC823/MPC823e. All variants include a separate RISC microengine called the [[Communication Processor Module|CPM]] that offloads communications processing tasks from the central processor and has functions for [[Direct memory access|DMA]]. The follow-on chip from this family, the MPC8260, has a 603e-based core and a different CPM.

Honda also uses PowerPC processors for its [[ASIMO]] robot.<ref>{{cite news|url=https://www.eetimes.com/latest-robots-fill-helper-entertainer-roles/|title=Latest robots fill helper, entertainer roles|date=28 November 2000|first=Yoshiko|last=Hara|publisher=EETimes.com|access-date=September 1, 2021|archive-date=September 1, 2021|archive-url=https://web.archive.org/web/20210901205052/https://www.eetimes.com/latest-robots-fill-helper-entertainer-roles/|url-status=live}}</ref>

In 2003, [[BAE Systems|BAE Systems Platform Solutions]] delivered the Vehicle-Management Computer for the [[Lockheed Martin F-35 Lightning II|F-35]] fighter jet. This platform consists of dual PowerPCs made by Freescale in a triple redundant setup.<ref>{{cite press release|url=http://news.lockheedmartin.com/2003-05-19-First-Lockheed-Martin-F-35-Joint-Strike-Fighter-Vehicle-Management-Computer-Delivered|title=First Lockheed Martin F-35 Joint Strike Fighter Vehicle-Management Computer Delivered|publisher=[[Lockheed Martin]]|date=May 16, 2003|access-date=January 14, 2018|archive-date=January 15, 2018|archive-url=https://web.archive.org/web/20180115071709/http://news.lockheedmartin.com/2003-05-19-First-Lockheed-Martin-F-35-Joint-Strike-Fighter-Vehicle-Management-Computer-Delivered|url-status=live}}</ref>

[[Aeronautical Development Establishment]] tested a high-performance digital flight control computer, powered by a quadraplex PowerPC-based processor setup on a [[HAL_Tejas#Tejas_Mark_1A|HAL Tejas Mark 1A]] in 2024.<ref>{{Cite news |date=2024-02-21 |title=Tejas combat jet flies successfully with home grown digital flight control computer |url=https://timesofindia.indiatimes.com/india/tejas-combat-jet-successfully-flies-with-home-grown-digital-flight-control-computer/articleshow/107859312.cms |access-date=2024-02-22 |work=The Times of India |issn=0971-8257}}</ref>