Editing Register renaming (section)

== History ==
The [[IBM System/360 Model 91]] was an early machine that supported out-of-order execution of instructions; it used the [[Tomasulo algorithm]], which uses register renaming.

The [[POWER1]] from 1990 is the first [[microprocessor]] that used register renaming and out-of-order execution. This processor implemented register renaming only for floating-point loads. The POWER1 had only one FPU, so using renaming for floating-point instructions other than memory operation was unnecessary. The [[POWER2]] had multiple FPUs, so renaming was used for all floating-point instructions.<ref name="simu"/>

The original [[R10000]] design had neither collapsing issue queues nor variable priority encoding, and suffered starvation problems as a result—the oldest instruction in the queue would sometimes not be issued until both instruction decode stopped completely for lack of rename registers, and every other instruction had been issued.
Later revisions of the design starting with the [[R10000#R12000|R12000]] used a partially variable priority encoder to mitigate this problem.

Early out-of-order machines did not separate the renaming and ROB/PRF storage functions.
For that matter, some of the earliest, such as Sohi's RUU or the Metaflow DCAF, combined scheduling, renaming, and storage all in the same structure.

Most modern machines do renaming by RAM indexing a map table with the logical register number.
E.g., P6 did this; future files do this, and have data storage in the same structure.

However, earlier machines used [[content-addressable memory]] (CAM) in the renamer.
E.g., the HPSM RAT, or Register Alias Table, essentially used a CAM on the logical register number in combination with different versions of the register.

In many ways, the story of out-of-order microarchitecture has been how these CAMs have been progressively eliminated.
Small CAMs are useful; large CAMs are impractical.{{Citation needed|date=October 2010}}

The [[P6 (microarchitecture)|P6 microarchitecture]] was the first microarchitecture by Intel to implement both out-of-order execution and register renaming.
The P6 microarchitecture was used in Pentium Pro, Pentium II, Pentium III, Pentium M, Core, and Core 2 microprocessors.
The [[Cyrix 6x86|Cyrix M1]], released on October 2, 1995,<ref name="cyrix"/> was the first x86 processor to use register renaming and out-of-order execution.
Other x86 processors (such as [[NexGen]] Nx686 and [[AMD K5]]) released in 1996 also featured register renaming and out-of-order execution of RISC [[Micro-operation|μ-operations]] (rather than native x86 instructions).<ref name="nx686"/><ref name="barr"/>