Editing Soft error (section)

=== Soft error mitigation===
A designer can attempt to minimize the rate of soft errors by judicious device design, choosing the right semiconductor, package and substrate materials, and the right device geometry. Often, however, this is limited by the need to reduce device size and voltage, to increase operating speed and to reduce power dissipation. The susceptibility of devices to upsets is described in the industry using the [[JEDEC]] [[JESD-89]] standard.

One technique that can be used to reduce the soft error rate in digital circuits is called [[radiation hardening]]. This involves increasing the
capacitance at selected circuit nodes in order to increase its effective Q<sub>crit</sub> value. This reduces the range of particle energies
to which the logic value of the node can be upset.  Radiation hardening is often accomplished by increasing the size of transistors who share
a drain/source region at the node.  Since the area and power overhead of radiation hardening can be restrictive to design, the technique is often applied selectively to nodes which are predicted to have the highest probability of resulting in soft errors if struck. Tools and models that can
predict which nodes are most vulnerable are the subject of past and current research in the area of soft errors.