Editing Subnormal number (section)

=== ARM ===
{{Unreferenced section|date=March 2023}}

AArch32 NEON (SIMD) FPU always uses a flush-to-zero mode{{cn|date=October 2024}}, which is the same as {{code|FTZ + DAZ}}. For the scalar FPU and in the AArch64 SIMD, the flush-to-zero behavior is optional and controlled by the {{code|FZ}} bit of the control register &ndash; FPSCR in Arm32 and FPCR in AArch64.<ref>{{cite web |url=https://developer.arm.com/documentation/ddi0595/2021-06/AArch64-Registers/FPCR--Floating-point-Control-Register?lang=en#fieldset_0-24_24 |title=Aarch64 Registers |publisher=Arm}}</ref>

One way to do this can be:

<syntaxhighlight lang="c">
#if defined(__arm64__) || defined(__aarch64__)
    uint64_t fpcr;
    asm( "mrs %0,   fpcr" : "=r"( fpcr ));             //Load the FPCR register
    asm( "msr fpcr, %0"   :: "r"( fpcr | (1 << 24) )); //Set the 24th bit (FTZ) to 1
#endif
</syntaxhighlight>

Some ARM processors have hardware handling of subnormals.