Editing Sum-addressed decoder (section)

==References==
* Paul Demone has an explanation of sum-addressed caches in a realworldtech [http://www.realworldtech.com/page.cfm?ArticleID=RWT091000000000 article].
* Heald et al.<ref>{{cite conference |last=Heald | first=R.| display-authors=etal |title=64 kB Sum-Addressed-Memory Cache with 1.6 ns Cycle and 2.6 ns Latency |book-title=ISSCC Digest of Technical Papers |pages=350–351 |year=1998 |doi=10.1109/ISSCC.1998.672519}}</ref> have a paper in ISSCC 1998 that explains what may be the original sum-addressed cache in the [[Ultrasparc]] III.
* Sum-addressed memory is described in
'''United States patent 5,754,819''',
May 19, 1998,
''Low-latency memory indexing method and structure''.
Inventors: Lynch; William L. (Palo Alto, CA), Lauterbach; Gary R. (Los Altos, CA);
Assignee: Sun Microsystems, Inc. (Mountain View, CA), Filed: July 28, 1994
* At least one of the inventors named on a patent related to carry-free address decoding credits the following publication:
''Evaluation of A + B = K Conditions without Carry Propagation'' (1992)
Jordi Cortadella, Jose M. Llaberia
'''IEEE Transactions on Computers''',
[http://citeseer.ist.psu.edu/565049.html] [http://citeseer.ist.psu.edu/cache/papers/cs/27410/http:zSzzSzwww.lsi.upc.eszSz~jordiczSzpublicationszSzpdfzSztc92_abk.pdf/cortadella92evaluation.pdf]
* The following patent extends this work, to use redundant form arithmetic throughout the processor, and so avoid carry propagation overhead even in ALU operations, or when an ALU operation is bypassed into a memory address:
'''United States Patent 5,619,664,'''
''Processor with architecture for improved pipelining of arithmetic instructions by forwarding redundant intermediate data forms'',
awarded April 18, 1997,
Inventor: Glew; Andrew F. (Hillsboro, OR);
Assignee: Intel Corporation (Santa Clara, CA),
Appl. No.: 08/402,322, Filed: March 10, 1995

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[[Category:Digital circuits]]