Editing Synchronous dynamic random-access memory (section)

== Construction and operation==
[[File:SDRAM_memory_module,_zoomed.jpg|thumb|SDRAM [[memory module]], zoomed]]
As an example, a 512&nbsp;MB SDRAM DIMM (which contains 512&nbsp;MB), might be made of eight or nine SDRAM chips, each containing 512&nbsp;Mbit of storage, and each one contributing 8 bits to the DIMM's 64- or 72-bit width. A typical 512&nbsp;Mbit SDRAM ''chip'' internally contains four independent 16&nbsp;MB memory banks. Each bank is an array of 8,192 rows of 16,384 bits each. (2048 8-bit columns). A bank is either idle, active, or changing from one to the other.{{binpre}}

The ''active'' command activates an idle bank. It presents a two-bit bank address (BA0&ndash;BA1) and a 13-bit row address (A0&ndash;A12), and causes a read of that row into the bank's array of all 16,384 column sense amplifiers. This is also known as "opening" the row. This operation has the side effect of [[Memory refresh|refresh]]ing the dynamic (capacitive) memory storage cells of that row.

Once the row has been activated or "opened", ''read'' and ''write'' commands are possible to that row. Activation requires a minimum amount of time, called the row-to-column delay, or t<sub>RCD</sub> before reads or writes to it may occur. This time, rounded up to the next multiple of the clock period, specifies the minimum number of wait cycles between an ''active'' command, and a ''read'' or ''write'' command. During these wait cycles, additional commands may be sent to other banks; because each bank operates completely independently.

Both ''read'' and ''write'' commands require a column address. Because each chip accesses eight bits of data at a time, there are 2,048 possible column addresses thus requiring only 11 address lines (A0&ndash;A9, A11).

When a ''read'' command is issued, the SDRAM will produce the corresponding output data on the DQ lines in time for the rising edge of the clock a few clock cycles later, depending on the configured CAS latency. Subsequent words of the burst will be produced in time for subsequent rising clock edges.

A ''write'' command is accompanied by the data to be written driven on to the DQ lines during the same rising clock edge. It is the duty of the memory controller to ensure that the SDRAM is not driving read data on to the DQ lines at the same time that it needs to drive write data on to those lines. This can be done by waiting until a read burst has finished, by terminating a read burst, or by using the DQM control line.

When the memory controller needs to access a different row, it must first return that bank's sense amplifiers to an idle state, ready to sense the next row. This is known as a "precharge" operation, or "closing" the row. A precharge may be commanded explicitly, or it may be performed automatically at the conclusion of a read or write operation. Again, there is a minimum time, the row precharge delay, t<sub>RP</sub>, which must elapse before that row is fully "closed" and so the bank is idle in order to receive another activate command on that bank.

Although refreshing a row is an automatic side effect of activating it, there is a minimum time for this to happen, which requires a minimum row access time t<sub>RAS</sub> delay between an ''active'' command opening a row, and the corresponding precharge command closing it. This limit is usually dwarfed by desired read and write commands to the row, so its value has little effect on typical performance.