Editing Test-and-set (section)

==Performance evaluation of test-and-set locks==

The four major evaluation metrics for locks in general are uncontended lock-acquisition latency, bus traffic, fairness, and storage.<ref name="Solihin">{{cite book|last1=Solihin|first1=Yan|title=Fundamentals of Parallel Architecture|date=2016|publisher=CRC Press|location=Boca Raton, FL|isbn=978-1-4822-1118-4}}</ref>

Test-and-set scores low on two of them, namely, high bus traffic and unfairness.

When processor P1 has obtained a lock and processor P2 is also waiting for the lock, P2 will keep incurring bus transactions in attempts to acquire the lock. When a processor has obtained a lock, all other processors which also wish to obtain the same lock keep trying to obtain the lock by initiating bus transactions repeatedly until they get hold of the lock. This increases the bus traffic requirement of test-and-set significantly. This slows down all other traffic from [[Cache (computing)|cache]] and [[Cache coherence|coherence]] misses. It slows down the overall section, since the traffic is saturated by failed lock acquisition attempts. [[Test and test-and-set|Test-and-test-and-set]] is an improvement over TSL since it does not initiate lock acquisition requests continuously.

When we consider fairness, we consider if a processor gets a fair chance of acquiring the lock when it is set free. In an extreme situation the processor might starve i.e. it might not be able to acquire the lock for an extended period of time even though it has become free during that time.

Storage overhead for TSL is next to nothing since only one lock is required. Uncontended latency is also low since only one atomic instruction and branch are needed.