Editing Zilog Z8000 (section)

===Memory handling===
Like the Z80, the Z8000 includes a system to automatically refresh [[dynamic RAM]]. In most systems this is normally handled by the [[video display controller]] or external logic. This was implemented via a separate Refresh Counter (RC) register that held the currently updating page of memory. The feature is turned on by setting the most significant bit of the RC, bit 15, to 1. The following six bits, 14 through 9 are a rate, measured in terms of every 4th clock cycle. With a standard 4&nbsp;MHz clock, that allows the refresh to be called every 1 to 64&nbsp;microseconds. The remaining 8 bits select a row in memory to refresh.<ref name="abramovitz1981"/>{{rp|pages=6.5,6.28}}

The Z8000 has a [[segmented memory]] map, with a 7-bit "segment number" and a 16-bit offset. Both numbers are represented by pins on the Z8001, meaning that it can directly address a 23-bit memory, or 8&nbsp;MB.<ref name="abramovitz1981"/>{{rp|pages=6.19}} Instructions can only directly access a 16-bit offset. This allows the instruction format to be smaller; a system with direct access to a 23-bit address would need to read three bytes (24 bits) from memory for every address referred to in the code, thus requiring two reads on a 16-bit bus. With segments, the addresses need only a single 16-bit read which is then added to a segment number to produce the complete address. The segment number only needs to be updated when the data crosses the 16-bit/64&nbsp;KB boundaries.<ref name="abramovitz1981"/>{{rp|pages=6.3}}

Internally, addresses are all 32 bits: an upper 16-bit word with a leading 0 in bit 15, the 7-bit segment number, and then 8 zeros. This requires more memory to store, as each 23-bit address uses up 32 bits of register space, but allows the addresses to be cleanly stored in the 16-bit registers and can be more easily pushed and popped from the stack, which occurs in 16-bit words.<ref name="abramovitz1981"/>{{rp|pages=6.6}}

The optional 48-pin Z8010 [[memory management unit]] (MMU) expands the memory map to 16&nbsp;MB by translating the 23-bit address from the CPU to a 24-bit one. A Z8010 has 64 segment descriptor registers, each of which contains a 16-bit base physical address, an 8-bit limit, and an 8-bit set of attributes. When the CPU attempts to access a particular segment, a 7-bit value, the Z8010 uses the lower 6 bits of the segment number to select a segment descriptor register, checks the 16-bit offset in the segment against the limit value in that register and checks the permission bits in the attributes to see whether the access is allowed and, if the access is allowed, adds the base physical address to the segment offset to generate a physical address. This allows multiple programs to be spread out in physical RAM, each given its own space to work in while believing it is accessing the entire 8&nbsp;MB of RAM. The segments are variable length, expanding up to 64&nbsp;KB in order to allow the entire memory to be accessed from 64 segments. If more than 64 segments are needed, multiple Z8010s can be used, with the upper bit of the 7-bit segment number selecting which Z8010 is used.<ref name="mmu">{{cite journal |author-last=Fawcett |author-first=B. K. |date=1983 |title=A tutorial overview of the Z8003 and Z8004 microprocessors and the Z8010 and Z8015 memory management units |journal=Journal of Microcomputer Applications |volume=6 |issue=2 |pages=163–178 |doi=10.1016/0745-7138(83)90028-3 }}</ref><ref name="mmu-datasheet">{{cite book |url=http://www.bitsavers.org/components/zilog/z8000/1988_Zilog_Z8000_Family_Data_Book.pdf |title=Z8000 Family Data Book |pages=163–178 |publisher=Zilog |date=November 1988}}</ref> The Z8010 was not available at the time of launch, and was ultimately nine months to a year late.{{sfn|OHP_2010_Z8000|p=20}}

With the release of the Z8003/Z8004, the Z8015 was added to the lineup, adding [[paged memory]] support. The main difference is that the Z8015 breaks down the memory into 64 2&nbsp;KB blocks, whereas the Z8010 broke memory into 64 variable-sized blocks, up to 64&nbsp;KB each. Additionally, the Z8015 expands the segment number from 7 to 12 bits, and then using those as the most significant bits of the 23-bit overall address, overriding the upper bits of the original 16-bit offset. The advantage to this access scheme is that it is easy to read or write 2&nbsp;KB blocks to a [[hard drive]], so this pattern more closely matches what will ultimately happen on a [[page fault]].<ref name="mmu"/>