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Adder (electronics)
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===3:2 compressors=== A full adder can be viewed as a ''3:2 lossy compressor'': it sums three one-bit inputs and returns the result as a single two-bit number; that is, it maps 8 input values to 4 output values. (the term "compressor" instead of "counter" was introduced in<ref>{{cite journal |first1=V.G. |last1=Oklobdzija |first2=D. |last2=Villeger |title=Improving Multiplier Design By Using Improved Column Compression Tree And Optimized Final Adder In CMOS Technology |journal=IEEE Transactions on VLSI Systems |volume=3 |issue=2 |date=June 1995 |pages=292β301 |doi=10.1109/92.386228 |url=https://www.acsel-lab.com/Publications/Papers/47-multipl-ieee-vlsi-95.pdf }}</ref>)Thus, for example, a binary input of 101 results in an output of {{nobr|1 + 0 + 1 {{=}} 10}} (decimal number 2). The carry-out represents bit one of the result, while the sum represents bit zero. Likewise, a half adder can be used as a ''2:2 lossy compressor'', compressing four possible inputs into three possible outputs. Such compressors can be used to speed up the summation of three or more addends. If the number of addends is exactly three, the layout is known as the [[carry-save adder]]. If the number of addends is four or more, more than one layer of compressors is necessary, and there are various possible designs for the circuit: the most common are [[Dadda tree|Dadda]] and [[Wallace tree]]s. This kind of circuit is most notably used in [[binary multiplier|multiplier circuits]], which is why these circuits are also known as Dadda and Wallace multipliers.
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