Editing Addressing mode (section)

===Sequential execution===
    +------+
    | nop  |              execute the following instruction
    +------+
 
    (Effective PC address = next instruction address)

The CPU, after executing a sequential instruction, immediately executes the following instruction.

Sequential execution is not considered to be an addressing mode on some computers.

Most instructions on most CPU architectures are sequential instructions. Because most instructions are sequential instructions, CPU designers often add features that deliberately sacrifice performance on the other instructions—branch instructions—in order to make these sequential instructions run faster.

Conditional branches load the PC with one of 2 possible results, depending on the condition—most CPU architectures use some other addressing mode for the "taken" branch, and sequential execution for the "not taken" branch.

Many features in modern CPUs—[[instruction prefetch]] and more complex [[pipeline (computing)|pipeline]]ing, [[out-of-order execution]], etc.—maintain the illusion that each instruction finishes before the next one begins, giving the same final results, even though that's not exactly what happens internally.

Each "[[basic block]]" of such sequential instructions exhibits both temporal and spatial [[locality of reference]].

====CPUs that do not use sequential execution====
CPUs that do not use sequential execution with a program counter are extremely rare. In some CPUs, each instruction always specifies the address of next instruction. Such CPUs have an instruction pointer that holds that specified address; it is not a program counter because there is no provision for incrementing it. Such CPUs include some [[drum memory]] computers such as the [[IBM 650]], the [[SECD machine]], [[LGP-30#RPC 4000|Librascope RPC 4000]], and the RTX 32P.<ref>{{cite web|url = http://www.ece.cmu.edu/~koopman/stack_computers/sec5_3.html |title =Architecture of the RTX 32P|work = Stack Computers|first = Philip|last= Koopman|date= 1989}}</ref>

On processors implemented with [[Microcode#Horizontal microcode|horizontal microcode]], the microinstruction may contain the high order bits of the next instruction address.

Other computing architectures go much further, attempting to bypass the [[von Neumann architecture#Von Neumann bottleneck|von Neumann bottleneck]] using a variety of [[program counter#Consequences in machine architecture|alternatives to the program counter]].