Editing Apollo Guidance Computer (section)

===Instruction set===

The [[instruction set|instruction format]] used 3 bits for [[opcode]], and 12 bits for address. Block I had 11 instructions: <code>TC</code>, <code>CCS</code>, <code>INDEX</code>, <code>XCH</code>, <code>CS</code>, <code>TS</code>, <code>AD</code>, and <code>MASK</code> (basic), and <code>SU</code>, <code>MP</code>, and <code>DV</code> (extra). The first eight, called ''basic instructions'', were directly accessed by the 3-bit op. code. The final three were denoted as ''extracode instructions'' because they were accessed by performing a special type of <code>TC</code> instruction (called <code>EXTEND</code>) immediately before the instruction.

The Block I AGC instructions consisted of the following:
;<code>TC</code> (transfer control): An unconditional branch to the address specified by the instruction. The return address was automatically stored in the Q register, so the <code>TC</code> instruction could be used for subroutine calls.
;<code>CCS</code> (count, compare, and skip): A complex conditional branch instruction. The A register was loaded with data retrieved from the address specified by the instruction. (Because the AGC uses [[ones' complement]] notation, there are two representations of zero. When all bits are set to zero, this is called ''plus zero''. If all bits are set to one, this is called ''minus zero''.) The ''diminished absolute value'' (DABS) of the data was then computed and stored in the A register. If the number was greater than zero, the DABS decrements the value by 1; if the number was negative, it is complemented before the decrement is applied—this is the absolute value. ''Diminished'' means "decremented but not below zero". Therefore, when the AGC performs the DABS function, positive numbers will head toward plus zero, and so will negative numbers but first revealing their negativity via the four-way skip below. The final step in <code>CCS</code> is a four-way skip, depending upon the data in register A before the DABS. If register A was greater than 0, <code>CCS</code> skips to the first instruction immediately after <code>CCS</code>. If register A contained plus zero, <code>CCS</code> skips to the second instruction after <code>CCS</code>. Less than zero causes a skip to the third instruction after <code>CCS</code>, and minus zero skips to the fourth instruction after <code>CCS</code>. The primary purpose of the count was to allow an ordinary loop, controlled by a positive counter, to end in a <code>CCS</code> and a <code>TC</code> to the beginning of the loop, equivalent to an [[System/360|IBM 360]]'s <code>BCT</code>. The absolute value function was deemed important enough to be built into this instruction; when used for only this purpose, the sequence after the <code>CCS</code> was <code>TC</code> *+2, <code>TC</code> *+2, <code>AD</code> ONE. A curious side effect was the creation and use of ''<code>CCS</code>-holes'' when the value being tested was known to be never positive, which occurred more often than one might suppose. That left two whole words unoccupied, and a special committee was responsible for assigning data constants to these holes.
;<code>INDEX</code>: Add the data retrieved at the address specified by the instruction to the next instruction. <code>INDEX</code> can be used to add or subtract an index value to the [[base address]] specified by the operand of the instruction that follows <code>INDEX</code>. This method is used to implement arrays and table look-ups; since the addition was done on both whole words, it was also used to modify the op. code in a following (extracode) instruction, and on rare occasions both functions at once.
;<code>RESUME</code>: A special instance of <code>INDEX</code> (<code>INDEX</code> 25). This is the instruction used to return from interrupts. It causes execution to resume at the interrupted location.
;<code>XCH</code> (exchange): Exchange the contents of memory with the contents of the A register. If the specified memory address is in fixed (read-only) memory, the memory contents are not affected, and this instruction simply loads register A. If it is in erasable memory, overflow "correction" is achieved by storing the leftmost of the 16 bits in A as the sign bit in memory, but there is no exceptional behavior like that of <code>TS</code>.
;<code>CS</code> (clear and subtract): Load register A with the ones' complement of the data referenced by the specified memory address.
;<code>TS</code> (transfer to storage): Store register A at the specified memory address. <code>TS</code> also detects, and corrects for, [[arithmetic overflow|overflow]]s in such a way as to propagate a carry for multi-precision add/subtract. If the result has no overflow (leftmost 2 bits of A the same), nothing special happens; if there is overflow (those 2 bits differ), the leftmost one goes the memory as the sign bit, register A is changed to +1 or −1 accordingly, and control skips to the second instruction following the <code>TS</code>. Whenever overflow is a possible but abnormal event, the <code>TS</code> was followed by a <code>TC</code> to the no-overflow logic; when it is a normal possibility (as in multi-precision add/subtract), the <code>TS</code> is followed by <code>CAF</code> ZERO (<code>CAF</code> = <code>XCH</code> to fixed memory) to complete the formation of the carry (+1, 0, or −1) into the next higher-precision word. Angles were kept in [[single precision]], distances and velocities in [[double precision]], and elapsed time in triple precision.
;<code>AD</code> (add): Add the contents of memory to register A and store the result in A. The 2 leftmost bits of A may be different (overflow state) before and/or after the <code>AD</code>. The fact that overflow is a state rather than an event forgives limited extents of overflow when adding more than two numbers, as long as none of the intermediate totals exceed twice the capacity of a word.
;<code>MASK</code>: Perform a bit-wise (boolean) ''and'' of memory with register A and store the result in register A.
;<code>MP</code> (multiply): Multiply the contents of register A by the data at the referenced memory address and store the high-order product in register A and the low-order product in register LP. The parts of the product agree in sign.
;<code>DV</code> (divide): Divide the contents of register A by the data at the referenced memory address. Store the quotient in register A and the absolute value of the remainder in register Q. Unlike modern machines, [[fixed-point arithmetic|fixed-point numbers]] were treated as fractions (notional decimal point just to right of the sign bit), so you could produce garbage if the divisor was not larger than the dividend; there was no protection against that situation. In the Block II AGC, a double-precision dividend started in A and L (the Block II LP), and the correctly signed remainder was delivered in L. That considerably simplified the subroutine for double precision division.
;<code>SU</code> (subtract): Subtract (ones' complement) the data at the referenced memory address from the contents of register A and store the result in A.

Instructions were implemented in groups of 12 steps, called ''timing pulses''. The timing pulses were named TP1 through TP12. Each set of 12 timing pulses was called an instruction ''subsequence''. Simple instructions, such as TC, executed in a single subsequence of 12 pulses. More complex instructions required several subsequences. The multiply instruction (<code>MP</code>) used 8 subsequences: an initial one called <code>MP0</code>, followed by an <code>MP1</code> subsequence which was repeated 6 times, and then terminated by an <code>MP3</code> subsequence. This was reduced to 3 subsequences in Block II.

Each timing pulse in a subsequence could trigger up to 5 ''control pulses''. The control pulses were the signals which did the actual work of the instruction, such as reading the contents of a register onto the bus, or writing data from the bus into a register.